clock-gating

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dianluniuniu / clock-management-unit

A comprehensive clock management IP core with multiple divider types and glitch-free switching

asic fpga verilog systemverilog digital-design amba apb clock-divider ip-core rtl-design clock-gating clock-management glitch-free-clock-mux

Updated Nov 2, 2025
Verilog

akhil-b-26 / parametric-low-power-alu-verilog

Star

A configurable Arithmetic Logic Unit (ALU) supporting 12 operations with parameterized data width. Designed with low-power techniques including clock gating and operand isolation. Simulated using Xilinx Vivado WebPACK with waveform verification.

verilog vlsi xilinx-vivado arithmetic-logic-unit parametric-design low-power-design clock-gating operand-isolation

Updated May 29, 2025
Verilog

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