Memory Architecture

Memory accesses: 0E 9E 06 8E 8F 0F FD ED 20 1E 16 EF 62 A0 21 68 A3 60 E7 EB 46 DD 05 9B 6D D5 5E 37 89 6E For each of direct mapped cache(DMC), fully associated cache(FAC), set associated cache (SAC) (4 ways), set associated cache (2 ways), run them with the give memory accesses and report the number of cache hits and misses. DMC ___ hits ____ misses FAC ___ hits ____ misses SAC 4 ways ___ hits ____ misses SAC 2 ways ___ hits ____ misses TLB Hits TLB Misses Page Hits Page Faults Implement FIFO cache block replacement algorithm (getFIFOCacheBlock) - remeasure and report the performance of FAC, SACsImplement FIFO page block replacement algorithm (getFIFORow) - remeasure and report the performance of Paging