diff --git a/library/SubcircuitLibrary/CA3002/CA3002-cache.lib b/library/SubcircuitLibrary/CA3002/CA3002-cache.lib new file mode 100644 index 000000000..7e9c6731b --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CA3002/CA3002.cir b/library/SubcircuitLibrary/CA3002/CA3002.cir new file mode 100644 index 000000000..d2a642ce8 --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002.cir @@ -0,0 +1,30 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\CA3002\CA3002.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 12/25/25 23:46:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_R10-Pad2_ 4.8k +R5 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 50 +R8 Net-_Q3-Pad1_ Net-_Q4-Pad3_ 50 +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN +R9 Net-_Q1-Pad1_ Net-_Q4-Pad1_ 3k +Q6 Net-_Q1-Pad1_ Net-_Q4-Pad1_ Net-_Q6-Pad3_ eSim_NPN +Q5 Net-_Q1-Pad1_ Net-_Q5-Pad2_ Net-_Q4-Pad2_ eSim_NPN +R11 Net-_Q6-Pad3_ Net-_R11-Pad2_ 2k +R10 Net-_Q4-Pad2_ Net-_R10-Pad2_ 4.8k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R1 Net-_Q3-Pad2_ Net-_R1-Pad2_ 5k +R3 Net-_Q3-Pad2_ Net-_D1-Pad1_ 2.8k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +R4 Net-_D2-Pad2_ Net-_R10-Pad2_ 2.2k +R6 Net-_Q3-Pad3_ Net-_R6-Pad2_ 500 +R7 Net-_R6-Pad2_ Net-_R10-Pad2_ 1k +U1 Net-_R1-Pad2_ Net-_R10-Pad2_ Net-_R6-Pad2_ Net-_D1-Pad1_ Net-_Q5-Pad2_ ? Net-_R11-Pad2_ Net-_Q6-Pad3_ Net-_Q1-Pad1_ Net-_Q1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/CA3002/CA3002.cir.out b/library/SubcircuitLibrary/CA3002/CA3002.cir.out new file mode 100644 index 000000000..880ec6188 --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002.cir.out @@ -0,0 +1,33 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3002\ca3002.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r10-pad2_ 4.8k +r5 net-_q2-pad3_ net-_q3-pad1_ 50 +r8 net-_q3-pad1_ net-_q4-pad3_ 50 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +r9 net-_q1-pad1_ net-_q4-pad1_ 3k +q6 net-_q1-pad1_ net-_q4-pad1_ net-_q6-pad3_ Q2N2222 +q5 net-_q1-pad1_ net-_q5-pad2_ net-_q4-pad2_ Q2N2222 +r11 net-_q6-pad3_ net-_r11-pad2_ 2k +r10 net-_q4-pad2_ net-_r10-pad2_ 4.8k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_q3-pad2_ net-_r1-pad2_ 5k +r3 net-_q3-pad2_ net-_d1-pad1_ 2.8k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +r4 net-_d2-pad2_ net-_r10-pad2_ 2.2k +r6 net-_q3-pad3_ net-_r6-pad2_ 500 +r7 net-_r6-pad2_ net-_r10-pad2_ 1k +* u1 net-_r1-pad2_ net-_r10-pad2_ net-_r6-pad2_ net-_d1-pad1_ net-_q5-pad2_ ? net-_r11-pad2_ net-_q6-pad3_ net-_q1-pad1_ net-_q1-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CA3002/CA3002.pro b/library/SubcircuitLibrary/CA3002/CA3002.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CA3002/CA3002.sch b/library/SubcircuitLibrary/CA3002/CA3002.sch new file mode 100644 index 000000000..13d5dad7c --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002.sch @@ -0,0 +1,490 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CA3002-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 694D7EC0 +P 2850 2850 +F 0 "Q1" H 2750 2900 50 0000 R CNN +F 1 "eSim_NPN" H 2800 3000 50 0000 R CNN +F 2 "" H 3050 2950 29 0000 C CNN +F 3 "" H 2850 2850 60 0000 C CNN + 1 2850 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 694D7EC1 +P 3350 3150 +F 0 "Q2" H 3250 3200 50 0000 R CNN +F 1 "eSim_NPN" H 3300 3300 50 0000 R CNN +F 2 "" H 3550 3250 29 0000 C CNN +F 3 "" H 3350 3150 60 0000 C CNN + 1 3350 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 694D7EC2 +P 2900 3400 +F 0 "R2" H 2950 3530 50 0000 C CNN +F 1 "4.8k" H 2950 3350 50 0000 C CNN +F 2 "" H 2950 3380 30 0000 C CNN +F 3 "" V 2950 3450 30 0000 C CNN + 1 2900 3400 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R5 +U 1 1 694D7EC3 +P 3750 3450 +F 0 "R5" H 3800 3580 50 0000 C CNN +F 1 "50" H 3800 3400 50 0000 C CNN +F 2 "" H 3800 3430 30 0000 C CNN +F 3 "" V 3800 3500 30 0000 C CNN + 1 3750 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 694D7EC4 +P 4350 3450 +F 0 "R8" H 4400 3580 50 0000 C CNN +F 1 "50" H 4400 3400 50 0000 C CNN +F 2 "" H 4400 3430 30 0000 C CNN +F 3 "" V 4400 3500 30 0000 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 694D7EC5 +P 4800 3150 +F 0 "Q4" H 4700 3200 50 0000 R CNN +F 1 "eSim_NPN" H 4750 3300 50 0000 R CNN +F 2 "" H 5000 3250 29 0000 C CNN +F 3 "" H 4800 3150 60 0000 C CNN + 1 4800 3150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2950 3050 2950 3300 +Wire Wire Line + 3150 3150 2950 3150 +Connection ~ 2950 3150 +Wire Wire Line + 3450 3350 3450 3400 +Wire Wire Line + 3450 3400 3650 3400 +Wire Wire Line + 3950 3400 4250 3400 +Wire Wire Line + 4700 3350 4700 3400 +Wire Wire Line + 4700 3400 4550 3400 +$Comp +L eSim_R R9 +U 1 1 694D7EC6 +P 4650 2150 +F 0 "R9" H 4700 2280 50 0000 C CNN +F 1 "3k" H 4700 2100 50 0000 C CNN +F 2 "" H 4700 2130 30 0000 C CNN +F 3 "" V 4700 2200 30 0000 C CNN + 1 4650 2150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4700 2350 4700 2950 +$Comp +L eSim_NPN Q6 +U 1 1 694D7EC7 +P 5600 2250 +F 0 "Q6" H 5500 2300 50 0000 R CNN +F 1 "eSim_NPN" H 5550 2400 50 0000 R CNN +F 2 "" H 5800 2350 29 0000 C CNN +F 3 "" H 5600 2250 60 0000 C CNN + 1 5600 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 694D7EC8 +P 5300 2650 +F 0 "Q5" H 5200 2700 50 0000 R CNN +F 1 "eSim_NPN" H 5250 2800 50 0000 R CNN +F 2 "" H 5500 2750 29 0000 C CNN +F 3 "" H 5300 2650 60 0000 C CNN + 1 5300 2650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5200 3150 +Wire Wire Line + 5200 3150 5000 3150 +Wire Wire Line + 5400 2250 4950 2250 +Wire Wire Line + 4950 2250 4950 2550 +Wire Wire Line + 4950 2550 4700 2550 +Connection ~ 4700 2550 +Wire Wire Line + 5200 2450 5200 2000 +Wire Wire Line + 2950 2000 5700 2000 +Wire Wire Line + 5700 2000 5700 2050 +Wire Wire Line + 4700 2000 4700 2050 +Connection ~ 5200 2000 +Wire Wire Line + 3450 2000 3450 2950 +Connection ~ 4700 2000 +Wire Wire Line + 2950 2000 2950 2650 +Connection ~ 3450 2000 +Wire Wire Line + 2650 2850 2500 2850 +Wire Wire Line + 2500 2850 2500 3000 +Wire Wire Line + 5500 2650 5600 2650 +Wire Wire Line + 5600 2650 5600 3400 +$Comp +L eSim_R R11 +U 1 1 694D7EC9 +P 5650 2800 +F 0 "R11" H 5700 2930 50 0000 C CNN +F 1 "2k" H 5700 2750 50 0000 C CNN +F 2 "" H 5700 2780 30 0000 C CNN +F 3 "" V 5700 2850 30 0000 C CNN + 1 5650 2800 + 0 1 1 0 +$EndComp +Wire Wire Line + 5700 2450 5700 2700 +Wire Wire Line + 5700 3000 5700 3400 +$Comp +L eSim_R R10 +U 1 1 694D7ECA +P 5000 3400 +F 0 "R10" H 5050 3530 50 0000 C CNN +F 1 "4.8k" H 5050 3350 50 0000 C CNN +F 2 "" H 5050 3380 30 0000 C CNN +F 3 "" V 5050 3450 30 0000 C CNN + 1 5000 3400 + 0 1 1 0 +$EndComp +Wire Wire Line + 5050 3300 5050 3150 +Connection ~ 5050 3150 +Wire Wire Line + 2950 3600 2950 3650 +Wire Wire Line + 2950 3650 5050 3650 +Wire Wire Line + 5050 5600 5050 3600 +$Comp +L eSim_NPN Q3 +U 1 1 694D7ECB +P 3950 3950 +F 0 "Q3" H 3850 4000 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4100 50 0000 R CNN +F 2 "" H 4150 4050 29 0000 C CNN +F 3 "" H 3950 3950 60 0000 C CNN + 1 3950 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4050 3400 4050 3750 +$Comp +L eSim_R R1 +U 1 1 694D7ECC +P 2800 4700 +F 0 "R1" H 2850 4830 50 0000 C CNN +F 1 "5k" H 2850 4650 50 0000 C CNN +F 2 "" H 2850 4680 30 0000 C CNN +F 3 "" V 2850 4750 30 0000 C CNN + 1 2800 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3750 3950 2850 3950 +Wire Wire Line + 2850 3950 2850 4600 +Wire Wire Line + 2850 4900 2850 5550 +$Comp +L eSim_R R3 +U 1 1 694D7ECD +P 3350 4250 +F 0 "R3" H 3400 4380 50 0000 C CNN +F 1 "2.8k" H 3400 4200 50 0000 C CNN +F 2 "" H 3400 4230 30 0000 C CNN +F 3 "" V 3400 4300 30 0000 C CNN + 1 3350 4250 + 0 1 1 0 +$EndComp +Wire Wire Line + 3400 4150 3400 3950 +Connection ~ 3400 3950 +$Comp +L eSim_Diode D1 +U 1 1 694D7ECE +P 3400 4700 +F 0 "D1" H 3400 4800 50 0000 C CNN +F 1 "eSim_Diode" H 3400 4600 50 0000 C CNN +F 2 "" H 3400 4700 60 0000 C CNN +F 3 "" H 3400 4700 60 0000 C CNN + 1 3400 4700 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 694D7ECF +P 3400 5050 +F 0 "D2" H 3400 5150 50 0000 C CNN +F 1 "eSim_Diode" H 3400 4950 50 0000 C CNN +F 2 "" H 3400 5050 60 0000 C CNN +F 3 "" H 3400 5050 60 0000 C CNN + 1 3400 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R4 +U 1 1 694D7ED0 +P 3350 5400 +F 0 "R4" H 3400 5530 50 0000 C CNN +F 1 "2.2k" H 3400 5350 50 0000 C CNN +F 2 "" H 3400 5380 30 0000 C CNN +F 3 "" V 3400 5450 30 0000 C CNN + 1 3350 5400 + 0 1 1 0 +$EndComp +Wire Wire Line + 3400 4450 3400 4550 +Wire Wire Line + 3400 4500 3150 4500 +Wire Wire Line + 3150 4500 3150 5550 +Connection ~ 3400 4500 +Wire Wire Line + 3400 4850 3400 4900 +Wire Wire Line + 3400 5200 3400 5300 +$Comp +L eSim_R R6 +U 1 1 694D7ED1 +P 4000 4350 +F 0 "R6" H 4050 4480 50 0000 C CNN +F 1 "500" H 4050 4300 50 0000 C CNN +F 2 "" H 4050 4330 30 0000 C CNN +F 3 "" V 4050 4400 30 0000 C CNN + 1 4000 4350 + 0 1 1 0 +$EndComp +Wire Wire Line + 4050 4150 4050 4250 +$Comp +L eSim_R R7 +U 1 1 694D7ED2 +P 4000 4950 +F 0 "R7" H 4050 5080 50 0000 C CNN +F 1 "1k" H 4050 4900 50 0000 C CNN +F 2 "" H 4050 4930 30 0000 C CNN +F 3 "" V 4050 5000 30 0000 C CNN + 1 4000 4950 + 0 1 1 0 +$EndComp +Wire Wire Line + 3400 5600 5050 5600 +Wire Wire Line + 4050 5600 4050 5150 +Wire Wire Line + 3750 5600 3750 5850 +Connection ~ 3750 5600 +Wire Wire Line + 4050 4850 4050 4550 +Wire Wire Line + 4050 4650 4450 4650 +Wire Wire Line + 4450 4650 4450 5800 +Connection ~ 4050 4650 +Connection ~ 5050 3650 +Connection ~ 4050 5600 +Connection ~ 4050 3400 +Wire Wire Line + 4050 2000 4050 1650 +Connection ~ 4050 2000 +Wire Wire Line + 5700 2550 6200 2550 +Connection ~ 5700 2550 +$Comp +L PORT U1 +U 1 1 694D7F00 +P 2600 5550 +F 0 "U1" H 2650 5650 30 0000 C CNN +F 1 "PORT" H 2600 5550 30 0000 C CNN +F 2 "" H 2600 5550 60 0000 C CNN +F 3 "" H 2600 5550 60 0000 C CNN + 1 2600 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 694D7FE6 +P 3500 5850 +F 0 "U1" H 3550 5950 30 0000 C CNN +F 1 "PORT" H 3500 5850 30 0000 C CNN +F 2 "" H 3500 5850 60 0000 C CNN +F 3 "" H 3500 5850 60 0000 C CNN + 2 3500 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 694D8068 +P 4200 5800 +F 0 "U1" H 4250 5900 30 0000 C CNN +F 1 "PORT" H 4200 5800 30 0000 C CNN +F 2 "" H 4200 5800 60 0000 C CNN +F 3 "" H 4200 5800 60 0000 C CNN + 3 4200 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 694D806E +P 2900 5550 +F 0 "U1" H 2950 5650 30 0000 C CNN +F 1 "PORT" H 2900 5550 30 0000 C CNN +F 2 "" H 2900 5550 60 0000 C CNN +F 3 "" H 2900 5550 60 0000 C CNN + 4 2900 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 694D8146 +P 5350 3400 +F 0 "U1" H 5400 3500 30 0000 C CNN +F 1 "PORT" H 5350 3400 30 0000 C CNN +F 2 "" H 5350 3400 60 0000 C CNN +F 3 "" H 5350 3400 60 0000 C CNN + 5 5350 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 694D814C +P 1350 3350 +F 0 "U1" H 1400 3450 30 0000 C CNN +F 1 "PORT" H 1350 3350 30 0000 C CNN +F 2 "" H 1350 3350 60 0000 C CNN +F 3 "" H 1350 3350 60 0000 C CNN + 6 1350 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 694D8152 +P 5700 3650 +F 0 "U1" H 5750 3750 30 0000 C CNN +F 1 "PORT" H 5700 3650 30 0000 C CNN +F 2 "" H 5700 3650 60 0000 C CNN +F 3 "" H 5700 3650 60 0000 C CNN + 7 5700 3650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 694D8158 +P 6200 2800 +F 0 "U1" H 6250 2900 30 0000 C CNN +F 1 "PORT" H 6200 2800 30 0000 C CNN +F 2 "" H 6200 2800 60 0000 C CNN +F 3 "" H 6200 2800 60 0000 C CNN + 8 6200 2800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 694D81C2 +P 3800 1650 +F 0 "U1" H 3850 1750 30 0000 C CNN +F 1 "PORT" H 3800 1650 30 0000 C CNN +F 2 "" H 3800 1650 60 0000 C CNN +F 3 "" H 3800 1650 60 0000 C CNN + 9 3800 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 694D81C8 +P 2250 3000 +F 0 "U1" H 2300 3100 30 0000 C CNN +F 1 "PORT" H 2250 3000 30 0000 C CNN +F 2 "" H 2250 3000 60 0000 C CNN +F 3 "" H 2250 3000 60 0000 C CNN + 10 2250 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 3350 1800 3350 +NoConn ~ 1800 3350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CA3002/CA3002.sub b/library/SubcircuitLibrary/CA3002/CA3002.sub new file mode 100644 index 000000000..a980330fc --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002.sub @@ -0,0 +1,27 @@ +* Subcircuit CA3002 +.subckt CA3002 net-_r1-pad2_ net-_r10-pad2_ net-_r6-pad2_ net-_d1-pad1_ net-_q5-pad2_ ? net-_r11-pad2_ net-_q6-pad3_ net-_q1-pad1_ net-_q1-pad2_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3002\ca3002.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r10-pad2_ 4.8k +r5 net-_q2-pad3_ net-_q3-pad1_ 50 +r8 net-_q3-pad1_ net-_q4-pad3_ 50 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +r9 net-_q1-pad1_ net-_q4-pad1_ 3k +q6 net-_q1-pad1_ net-_q4-pad1_ net-_q6-pad3_ Q2N2222 +q5 net-_q1-pad1_ net-_q5-pad2_ net-_q4-pad2_ Q2N2222 +r11 net-_q6-pad3_ net-_r11-pad2_ 2k +r10 net-_q4-pad2_ net-_r10-pad2_ 4.8k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_q3-pad2_ net-_r1-pad2_ 5k +r3 net-_q3-pad2_ net-_d1-pad1_ 2.8k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +r4 net-_d2-pad2_ net-_r10-pad2_ 2.2k +r6 net-_q3-pad3_ net-_r6-pad2_ 500 +r7 net-_r6-pad2_ net-_r10-pad2_ 1k +* Control Statements + +.ends CA3002 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3002/CA3002_Previous_Values.xml b/library/SubcircuitLibrary/CA3002/CA3002_Previous_Values.xml new file mode 100644 index 000000000..f1309427f --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/CA3002_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3002/D.lib b/library/SubcircuitLibrary/CA3002/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/CA3002/NPN.lib b/library/SubcircuitLibrary/CA3002/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/CA3002/analysis b/library/SubcircuitLibrary/CA3002/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CA3002/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3021/CA3021-cache.lib b/library/SubcircuitLibrary/CA3021/CA3021-cache.lib new file mode 100644 index 000000000..7e9c6731b --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CA3021/CA3021.cir b/library/SubcircuitLibrary/CA3021/CA3021.cir new file mode 100644 index 000000000..d19ddd428 --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021.cir @@ -0,0 +1,33 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\CA3021\CA3021.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/26 20:30:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q1-Pad1_ Net-_R1-Pad2_ 3.9k +R3 Net-_Q1-Pad2_ Net-_R1-Pad2_ 15k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_R1-Pad2_ Net-_D1-Pad1_ 3.9k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R11-Pad1_ Net-_Q1-Pad1_ 34k +R6 Net-_R11-Pad1_ Net-_Q3-Pad1_ 0.1k +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q2-Pad2_ Net-_D1-Pad2_ eSim_NPN +R4 Net-_Q2-Pad2_ Net-_R4-Pad2_ 5k +R9 Net-_Q5-Pad2_ Net-_R4-Pad2_ 5k +R7 Net-_D3-Pad2_ Net-_D1-Pad2_ 3.9k +R8 Net-_R4-Pad2_ Net-_R8-Pad2_ 5k +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_D1-Pad2_ eSim_NPN +R10 Net-_Q4-Pad3_ Net-_Q5-Pad1_ 0.75k +Q4 Net-_Q4-Pad1_ Net-_D3-Pad2_ Net-_Q4-Pad3_ eSim_NPN +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +R11 Net-_R11-Pad1_ Net-_Q4-Pad1_ 75k +Q6 Net-_Q6-Pad1_ Net-_Q4-Pad1_ Net-_Q6-Pad3_ eSim_NPN +R12 Net-_R11-Pad1_ Net-_Q6-Pad1_ 0.3k +R13 Net-_Q6-Pad3_ Net-_D1-Pad2_ 3.9k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +U1 Net-_Q1-Pad2_ Net-_R8-Pad2_ Net-_Q1-Pad1_ Net-_D2-Pad1_ Net-_R11-Pad1_ Net-_D2-Pad2_ Net-_Q4-Pad1_ Net-_Q6-Pad3_ Net-_D3-Pad1_ Net-_Q5-Pad1_ Net-_D1-Pad2_ Net-_Q1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CA3021/CA3021.cir.out b/library/SubcircuitLibrary/CA3021/CA3021.cir.out new file mode 100644 index 000000000..18756eae4 --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021.cir.out @@ -0,0 +1,36 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3021\ca3021.cir + +.include NPN.lib +.include D.lib +r1 net-_q1-pad1_ net-_r1-pad2_ 3.9k +r3 net-_q1-pad2_ net-_r1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_r1-pad2_ net-_d1-pad1_ 3.9k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r11-pad1_ net-_q1-pad1_ 34k +r6 net-_r11-pad1_ net-_q3-pad1_ 0.1k +q3 net-_q3-pad1_ net-_q1-pad1_ net-_d3-pad2_ Q2N2222 +q2 net-_q1-pad3_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r4 net-_q2-pad2_ net-_r4-pad2_ 5k +r9 net-_q5-pad2_ net-_r4-pad2_ 5k +r7 net-_d3-pad2_ net-_d1-pad2_ 3.9k +r8 net-_r4-pad2_ net-_r8-pad2_ 5k +q5 net-_q5-pad1_ net-_q5-pad2_ net-_d1-pad2_ Q2N2222 +r10 net-_q4-pad3_ net-_q5-pad1_ 0.75k +q4 net-_q4-pad1_ net-_d3-pad2_ net-_q4-pad3_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +r11 net-_r11-pad1_ net-_q4-pad1_ 75k +q6 net-_q6-pad1_ net-_q4-pad1_ net-_q6-pad3_ Q2N2222 +r12 net-_r11-pad1_ net-_q6-pad1_ 0.3k +r13 net-_q6-pad3_ net-_d1-pad2_ 3.9k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +* u1 net-_q1-pad2_ net-_r8-pad2_ net-_q1-pad1_ net-_d2-pad1_ net-_r11-pad1_ net-_d2-pad2_ net-_q4-pad1_ net-_q6-pad3_ net-_d3-pad1_ net-_q5-pad1_ net-_d1-pad2_ net-_q1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CA3021/CA3021.pro b/library/SubcircuitLibrary/CA3021/CA3021.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CA3021/CA3021.sch b/library/SubcircuitLibrary/CA3021/CA3021.sch new file mode 100644 index 000000000..52d7de2be --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021.sch @@ -0,0 +1,557 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CA3021-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R1 +U 1 1 69625C2F +P 3250 3700 +F 0 "R1" H 3300 3830 50 0000 C CNN +F 1 "3.9k" H 3300 3650 50 0000 C CNN +F 2 "" H 3300 3680 30 0000 C CNN +F 3 "" V 3300 3750 30 0000 C CNN + 1 3250 3700 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 69625C30 +P 3650 3700 +F 0 "R3" H 3700 3830 50 0000 C CNN +F 1 "15k" H 3700 3650 50 0000 C CNN +F 2 "" H 3700 3680 30 0000 C CNN +F 3 "" V 3700 3750 30 0000 C CNN + 1 3650 3700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 69625C31 +P 4200 3550 +F 0 "Q1" H 4100 3600 50 0000 R CNN +F 1 "eSim_NPN" H 4150 3700 50 0000 R CNN +F 2 "" H 4400 3650 29 0000 C CNN +F 3 "" H 4200 3550 60 0000 C CNN + 1 4200 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 69625C32 +P 3450 4150 +F 0 "R2" H 3500 4280 50 0000 C CNN +F 1 "3.9k" H 3500 4100 50 0000 C CNN +F 2 "" H 3500 4130 30 0000 C CNN +F 3 "" V 3500 4200 30 0000 C CNN + 1 3450 4150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 69625C33 +P 3500 4550 +F 0 "D1" H 3500 4650 50 0000 C CNN +F 1 "eSim_Diode" H 3500 4450 50 0000 C CNN +F 2 "" H 3500 4550 60 0000 C CNN +F 3 "" H 3500 4550 60 0000 C CNN + 1 3500 4550 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R5 +U 1 1 69625C34 +P 4000 2450 +F 0 "R5" H 4050 2580 50 0000 C CNN +F 1 "34k" H 4050 2400 50 0000 C CNN +F 2 "" H 4050 2430 30 0000 C CNN +F 3 "" V 4050 2500 30 0000 C CNN + 1 4000 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 69625C35 +P 4850 2150 +F 0 "R6" H 4900 2280 50 0000 C CNN +F 1 "0.1k" H 4900 2100 50 0000 C CNN +F 2 "" H 4900 2130 30 0000 C CNN +F 3 "" V 4900 2200 30 0000 C CNN + 1 4850 2150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 69625C36 +P 4800 2700 +F 0 "Q3" H 4700 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4750 2850 50 0000 R CNN +F 2 "" H 5000 2800 29 0000 C CNN +F 3 "" H 4800 2700 60 0000 C CNN + 1 4800 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 69625C37 +P 4200 4800 +F 0 "Q2" H 4100 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4150 4950 50 0000 R CNN +F 2 "" H 4400 4900 29 0000 C CNN +F 3 "" H 4200 4800 60 0000 C CNN + 1 4200 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3900 3300 4000 +Wire Wire Line + 3300 4000 3700 4000 +Wire Wire Line + 3700 4000 3700 3900 +Wire Wire Line + 3700 3600 3700 3550 +Wire Wire Line + 2650 3550 4000 3550 +Connection ~ 3700 3550 +Wire Wire Line + 3500 4050 3500 4000 +Connection ~ 3500 4000 +Wire Wire Line + 3500 4350 3500 4400 +Wire Wire Line + 3500 4700 3500 5900 +Wire Wire Line + 3300 3600 3300 2700 +Wire Wire Line + 3300 2700 4600 2700 +Wire Wire Line + 4300 2700 4300 3350 +Wire Wire Line + 4050 2650 4050 2700 +Connection ~ 4050 2700 +Wire Wire Line + 4500 2700 4500 1700 +Connection ~ 4300 2700 +Wire Wire Line + 4050 2350 4050 1950 +Wire Wire Line + 4050 1950 6350 1950 +Wire Wire Line + 4900 1950 4900 2050 +Wire Wire Line + 4900 2500 4900 2350 +Connection ~ 4500 2700 +Wire Wire Line + 4300 3750 4300 4600 +Wire Wire Line + 4300 5000 4300 5050 +Wire Wire Line + 3500 5050 6200 5050 +Connection ~ 3500 5050 +$Comp +L eSim_R R4 +U 1 1 69625C38 +P 3850 5250 +F 0 "R4" H 3900 5380 50 0000 C CNN +F 1 "5k" H 3900 5200 50 0000 C CNN +F 2 "" H 3900 5230 30 0000 C CNN +F 3 "" V 3900 5300 30 0000 C CNN + 1 3850 5250 + 0 1 1 0 +$EndComp +Wire Wire Line + 3900 4800 3900 5150 +Wire Wire Line + 3900 4800 4000 4800 +Wire Wire Line + 4300 4450 4600 4450 +Wire Wire Line + 4600 4450 4600 5950 +Connection ~ 4300 4450 +Wire Wire Line + 3900 5450 3900 5550 +Wire Wire Line + 3900 5550 5050 5550 +Wire Wire Line + 5050 5550 5050 5450 +$Comp +L eSim_R R9 +U 1 1 69625C39 +P 5000 5250 +F 0 "R9" H 5050 5380 50 0000 C CNN +F 1 "5k" H 5050 5200 50 0000 C CNN +F 2 "" H 5050 5230 30 0000 C CNN +F 3 "" V 5050 5300 30 0000 C CNN + 1 5000 5250 + 0 1 1 0 +$EndComp +Wire Wire Line + 4900 4400 4900 5050 +Connection ~ 4300 5050 +$Comp +L eSim_R R7 +U 1 1 69625C3A +P 4850 4200 +F 0 "R7" H 4900 4330 50 0000 C CNN +F 1 "3.9k" H 4900 4150 50 0000 C CNN +F 2 "" H 4900 4180 30 0000 C CNN +F 3 "" V 4900 4250 30 0000 C CNN + 1 4850 4200 + 0 1 1 0 +$EndComp +Wire Wire Line + 4900 2900 4900 4100 +$Comp +L eSim_R R8 +U 1 1 69625C3B +P 4850 5700 +F 0 "R8" H 4900 5830 50 0000 C CNN +F 1 "5k" H 4900 5650 50 0000 C CNN +F 2 "" H 4900 5680 30 0000 C CNN +F 3 "" V 4900 5750 30 0000 C CNN + 1 4850 5700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4900 5600 4900 5550 +Connection ~ 4900 5550 +Wire Wire Line + 4900 5900 4900 5950 +$Comp +L eSim_NPN Q5 +U 1 1 69625C3C +P 5250 4800 +F 0 "Q5" H 5150 4850 50 0000 R CNN +F 1 "eSim_NPN" H 5200 4950 50 0000 R CNN +F 2 "" H 5450 4900 29 0000 C CNN +F 3 "" H 5250 4800 60 0000 C CNN + 1 5250 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 5050 5350 5000 +Connection ~ 4900 5050 +Wire Wire Line + 5050 4800 5050 5150 +$Comp +L eSim_R R10 +U 1 1 69625C3D +P 5300 4200 +F 0 "R10" H 5350 4330 50 0000 C CNN +F 1 "0.75k" H 5350 4150 50 0000 C CNN +F 2 "" H 5350 4180 30 0000 C CNN +F 3 "" V 5350 4250 30 0000 C CNN + 1 5300 4200 + 0 1 1 0 +$EndComp +Wire Wire Line + 5350 4400 5350 4600 +$Comp +L eSim_NPN Q4 +U 1 1 69625C3E +P 5250 3700 +F 0 "Q4" H 5150 3750 50 0000 R CNN +F 1 "eSim_NPN" H 5200 3850 50 0000 R CNN +F 2 "" H 5450 3800 29 0000 C CNN +F 3 "" H 5250 3700 60 0000 C CNN + 1 5250 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3900 5350 4100 +Wire Wire Line + 4900 3700 5050 3700 +Connection ~ 4900 3700 +Wire Wire Line + 5000 3700 5000 4000 +Wire Wire Line + 5000 4000 5650 4000 +Connection ~ 5000 3700 +$Comp +L eSim_Diode D3 +U 1 1 69625C3F +P 5800 4000 +F 0 "D3" H 5800 4100 50 0000 C CNN +F 1 "eSim_Diode" H 5800 3900 50 0000 C CNN +F 2 "" H 5800 4000 60 0000 C CNN +F 3 "" H 5800 4000 60 0000 C CNN + 1 5800 4000 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 4000 6600 4000 +Connection ~ 4900 1950 +Wire Wire Line + 5350 3500 5350 2800 +Wire Wire Line + 5200 1700 5200 2800 +Wire Wire Line + 5200 2800 5900 2800 +Connection ~ 5350 2800 +Wire Wire Line + 5550 1950 5550 2100 +Connection ~ 5550 1950 +$Comp +L eSim_R R11 +U 1 1 69625C40 +P 5500 2200 +F 0 "R11" H 5550 2330 50 0000 C CNN +F 1 "75k" H 5550 2150 50 0000 C CNN +F 2 "" H 5550 2180 30 0000 C CNN +F 3 "" V 5550 2250 30 0000 C CNN + 1 5500 2200 + 0 1 1 0 +$EndComp +Wire Wire Line + 5550 2400 5550 2800 +Connection ~ 5550 2800 +$Comp +L eSim_NPN Q6 +U 1 1 69625C41 +P 6100 2800 +F 0 "Q6" H 6000 2850 50 0000 R CNN +F 1 "eSim_NPN" H 6050 2950 50 0000 R CNN +F 2 "" H 6300 2900 29 0000 C CNN +F 3 "" H 6100 2800 60 0000 C CNN + 1 6100 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R12 +U 1 1 69625C42 +P 6150 2250 +F 0 "R12" H 6200 2380 50 0000 C CNN +F 1 "0.3k" H 6200 2200 50 0000 C CNN +F 2 "" H 6200 2230 30 0000 C CNN +F 3 "" V 6200 2300 30 0000 C CNN + 1 6150 2250 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 2600 6200 2450 +Wire Wire Line + 6200 2150 6200 1950 +Connection ~ 6200 1950 +$Comp +L eSim_R R13 +U 1 1 69625C43 +P 6150 3200 +F 0 "R13" H 6200 3330 50 0000 C CNN +F 1 "3.9k" H 6200 3150 50 0000 C CNN +F 2 "" H 6200 3180 30 0000 C CNN +F 3 "" V 6200 3250 30 0000 C CNN + 1 6150 3200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 3000 6200 3100 +Wire Wire Line + 6200 5050 6200 3400 +Connection ~ 5350 5050 +Wire Wire Line + 5350 4500 5900 4500 +Wire Wire Line + 5900 4500 5900 5950 +Connection ~ 5350 4500 +Wire Wire Line + 6200 3050 6600 3050 +Connection ~ 6200 3050 +$Comp +L eSim_Diode D2 +U 1 1 69625C44 +P 4850 1300 +F 0 "D2" H 4850 1400 50 0000 C CNN +F 1 "eSim_Diode" H 4850 1200 50 0000 C CNN +F 2 "" H 4850 1300 60 0000 C CNN +F 3 "" H 4850 1300 60 0000 C CNN + 1 4850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 1300 5100 1300 +Wire Wire Line + 4700 1300 4550 1300 +$Comp +L PORT U1 +U 1 1 69625C78 +P 2400 3550 +F 0 "U1" H 2450 3650 30 0000 C CNN +F 1 "PORT" H 2400 3550 30 0000 C CNN +F 2 "" H 2400 3550 60 0000 C CNN +F 3 "" H 2400 3550 60 0000 C CNN + 1 2400 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 69625D71 +P 4900 6200 +F 0 "U1" H 4950 6300 30 0000 C CNN +F 1 "PORT" H 4900 6200 30 0000 C CNN +F 2 "" H 4900 6200 60 0000 C CNN +F 3 "" H 4900 6200 60 0000 C CNN + 2 4900 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 69625DD9 +P 4250 1700 +F 0 "U1" H 4300 1800 30 0000 C CNN +F 1 "PORT" H 4250 1700 30 0000 C CNN +F 2 "" H 4250 1700 60 0000 C CNN +F 3 "" H 4250 1700 60 0000 C CNN + 3 4250 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 69625DDF +P 4300 1300 +F 0 "U1" H 4350 1400 30 0000 C CNN +F 1 "PORT" H 4300 1300 30 0000 C CNN +F 2 "" H 4300 1300 60 0000 C CNN +F 3 "" H 4300 1300 60 0000 C CNN + 4 4300 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 69625E9D +P 6350 2200 +F 0 "U1" H 6400 2300 30 0000 C CNN +F 1 "PORT" H 6350 2200 30 0000 C CNN +F 2 "" H 6350 2200 60 0000 C CNN +F 3 "" H 6350 2200 60 0000 C CNN + 5 6350 2200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 69625EA3 +P 5350 1300 +F 0 "U1" H 5400 1400 30 0000 C CNN +F 1 "PORT" H 5350 1300 30 0000 C CNN +F 2 "" H 5350 1300 60 0000 C CNN +F 3 "" H 5350 1300 60 0000 C CNN + 6 5350 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 69625EA9 +P 4950 1700 +F 0 "U1" H 5000 1800 30 0000 C CNN +F 1 "PORT" H 4950 1700 30 0000 C CNN +F 2 "" H 4950 1700 60 0000 C CNN +F 3 "" H 4950 1700 60 0000 C CNN + 7 4950 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 69625EAF +P 6600 3300 +F 0 "U1" H 6650 3400 30 0000 C CNN +F 1 "PORT" H 6600 3300 30 0000 C CNN +F 2 "" H 6600 3300 60 0000 C CNN +F 3 "" H 6600 3300 60 0000 C CNN + 8 6600 3300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 69625FCF +P 6600 4250 +F 0 "U1" H 6650 4350 30 0000 C CNN +F 1 "PORT" H 6600 4250 30 0000 C CNN +F 2 "" H 6600 4250 60 0000 C CNN +F 3 "" H 6600 4250 60 0000 C CNN + 9 6600 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 69625FD5 +P 5650 5950 +F 0 "U1" H 5700 6050 30 0000 C CNN +F 1 "PORT" H 5650 5950 30 0000 C CNN +F 2 "" H 5650 5950 60 0000 C CNN +F 3 "" H 5650 5950 60 0000 C CNN + 10 5650 5950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69625FDB +P 3250 5900 +F 0 "U1" H 3300 6000 30 0000 C CNN +F 1 "PORT" H 3250 5900 30 0000 C CNN +F 2 "" H 3250 5900 60 0000 C CNN +F 3 "" H 3250 5900 60 0000 C CNN + 11 3250 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 69625FE1 +P 4350 5950 +F 0 "U1" H 4400 6050 30 0000 C CNN +F 1 "PORT" H 4350 5950 30 0000 C CNN +F 2 "" H 4350 5950 60 0000 C CNN +F 3 "" H 4350 5950 60 0000 C CNN + 12 4350 5950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CA3021/CA3021.sub b/library/SubcircuitLibrary/CA3021/CA3021.sub new file mode 100644 index 000000000..5774851da --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021.sub @@ -0,0 +1,30 @@ +* Subcircuit CA3021 +.subckt CA3021 net-_q1-pad2_ net-_r8-pad2_ net-_q1-pad1_ net-_d2-pad1_ net-_r11-pad1_ net-_d2-pad2_ net-_q4-pad1_ net-_q6-pad3_ net-_d3-pad1_ net-_q5-pad1_ net-_d1-pad2_ net-_q1-pad3_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3021\ca3021.cir +.include NPN.lib +.include D.lib +r1 net-_q1-pad1_ net-_r1-pad2_ 3.9k +r3 net-_q1-pad2_ net-_r1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_r1-pad2_ net-_d1-pad1_ 3.9k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r11-pad1_ net-_q1-pad1_ 34k +r6 net-_r11-pad1_ net-_q3-pad1_ 0.1k +q3 net-_q3-pad1_ net-_q1-pad1_ net-_d3-pad2_ Q2N2222 +q2 net-_q1-pad3_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r4 net-_q2-pad2_ net-_r4-pad2_ 5k +r9 net-_q5-pad2_ net-_r4-pad2_ 5k +r7 net-_d3-pad2_ net-_d1-pad2_ 3.9k +r8 net-_r4-pad2_ net-_r8-pad2_ 5k +q5 net-_q5-pad1_ net-_q5-pad2_ net-_d1-pad2_ Q2N2222 +r10 net-_q4-pad3_ net-_q5-pad1_ 0.75k +q4 net-_q4-pad1_ net-_d3-pad2_ net-_q4-pad3_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +r11 net-_r11-pad1_ net-_q4-pad1_ 75k +q6 net-_q6-pad1_ net-_q4-pad1_ net-_q6-pad3_ Q2N2222 +r12 net-_r11-pad1_ net-_q6-pad1_ 0.3k +r13 net-_q6-pad3_ net-_d1-pad2_ 3.9k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +* Control Statements + +.ends CA3021 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3021/CA3021_Previous_Values.xml b/library/SubcircuitLibrary/CA3021/CA3021_Previous_Values.xml new file mode 100644 index 000000000..c66b377af --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/CA3021_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3021/D.lib b/library/SubcircuitLibrary/CA3021/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/CA3021/NPN.lib b/library/SubcircuitLibrary/CA3021/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/CA3021/analysis b/library/SubcircuitLibrary/CA3021/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CA3021/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3085/CA3085-cache.lib b/library/SubcircuitLibrary/CA3085/CA3085-cache.lib new file mode 100644 index 000000000..159864cb0 --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CA3085/CA3085.cir b/library/SubcircuitLibrary/CA3085/CA3085.cir new file mode 100644 index 000000000..50ec6d13e --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085.cir @@ -0,0 +1,33 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\CA3085\CA3085.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 12/21/25 19:14:37 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_D2-Pad1_ Net-_D1-Pad1_ 40k +U2 Net-_D3-Pad2_ Net-_D1-Pad1_ zener +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 Net-_D1-Pad2_ Net-_Q1-Pad2_ Net-_D2-Pad2_ eSim_PNP +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +U3 Net-_D3-Pad2_ Net-_D1-Pad2_ zener +Q2 Net-_Q1-Pad2_ Net-_D2-Pad2_ Net-_D2-Pad1_ eSim_PNP +Q3 Net-_Q1-Pad2_ Net-_D1-Pad2_ ? eSim_NPN +R2 ? Net-_Q4-Pad2_ 4k +R3 Net-_Q4-Pad2_ Net-_D3-Pad1_ 1.5k +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q5 Net-_Q4-Pad1_ Net-_D4-Pad2_ Net-_D2-Pad1_ eSim_PNP +D4 Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q7 Net-_Q10-Pad2_ Net-_Q4-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q8 Net-_Q10-Pad2_ Net-_Q8-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q6 Net-_Q4-Pad3_ Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q10 Net-_D2-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q9 Net-_Q10-Pad2_ Net-_Q9-Pad2_ Net-_Q9-Pad3_ eSim_NPN +R4 Net-_Q9-Pad2_ Net-_Q11-Pad3_ 1.5k +Q11 Net-_Q11-Pad1_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R5 Net-_D2-Pad1_ Net-_Q11-Pad1_ 500 +U1 Net-_Q11-Pad3_ Net-_Q11-Pad1_ Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_Q4-Pad2_ Net-_Q8-Pad2_ Net-_Q10-Pad2_ Net-_Q9-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CA3085/CA3085.cir.out b/library/SubcircuitLibrary/CA3085/CA3085.cir.out new file mode 100644 index 000000000..14341b0ef --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085.cir.out @@ -0,0 +1,43 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3085\ca3085.cir + +.include D.lib +.include PNP.lib +.include NPN.lib +r1 net-_d2-pad1_ net-_d1-pad1_ 40k +* u2 net-_d3-pad2_ net-_d1-pad1_ zener +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_d1-pad2_ net-_q1-pad2_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +* u3 net-_d3-pad2_ net-_d1-pad2_ zener +q2 net-_q1-pad2_ net-_d2-pad2_ net-_d2-pad1_ Q2N2907A +q3 net-_q1-pad2_ net-_d1-pad2_ ? Q2N2222 +r2 ? net-_q4-pad2_ 4k +r3 net-_q4-pad2_ net-_d3-pad1_ 1.5k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q4-pad1_ net-_d4-pad2_ net-_d2-pad1_ Q2N2907A +d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148 +q7 net-_q10-pad2_ net-_q4-pad1_ net-_d4-pad2_ Q2N2907A +q8 net-_q10-pad2_ net-_q8-pad2_ net-_q4-pad3_ Q2N2222 +q6 net-_q4-pad3_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +q10 net-_d2-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q9 net-_q10-pad2_ net-_q9-pad2_ net-_q9-pad3_ Q2N2222 +r4 net-_q9-pad2_ net-_q11-pad3_ 1.5k +q11 net-_q11-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r5 net-_d2-pad1_ net-_q11-pad1_ 500 +* u1 net-_q11-pad3_ net-_q11-pad1_ net-_d2-pad1_ net-_d3-pad2_ net-_q4-pad2_ net-_q8-pad2_ net-_q10-pad2_ net-_q9-pad3_ port +a1 net-_d3-pad2_ net-_d1-pad1_ u2 +a2 net-_d3-pad2_ net-_d1-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CA3085/CA3085.pro b/library/SubcircuitLibrary/CA3085/CA3085.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CA3085/CA3085.sch b/library/SubcircuitLibrary/CA3085/CA3085.sch new file mode 100644 index 000000000..14bf91777 --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085.sch @@ -0,0 +1,520 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CA3085-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R1 +U 1 1 6947F8DD +P 2900 2900 +F 0 "R1" H 2950 3030 50 0000 C CNN +F 1 "40k" H 2950 2850 50 0000 C CNN +F 2 "" H 2950 2880 30 0000 C CNN +F 3 "" V 2950 2950 30 0000 C CNN + 1 2900 2900 + 0 1 1 0 +$EndComp +$Comp +L zener U2 +U 1 1 6947F8DE +P 2950 4350 +F 0 "U2" H 2900 4250 60 0000 C CNN +F 1 "zener" H 2950 4450 60 0000 C CNN +F 2 "" H 3000 4350 60 0000 C CNN +F 3 "" H 3000 4350 60 0000 C CNN + 1 2950 4350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6947F8DF +P 3150 3550 +F 0 "D1" H 3150 3650 50 0000 C CNN +F 1 "eSim_Diode" H 3150 3450 50 0000 C CNN +F 2 "" H 3150 3550 60 0000 C CNN +F 3 "" H 3150 3550 60 0000 C CNN + 1 3150 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6947F8E0 +P 3300 2850 +F 0 "Q1" H 3200 2900 50 0000 R CNN +F 1 "eSim_PNP" H 3250 3000 50 0000 R CNN +F 2 "" H 3500 2950 29 0000 C CNN +F 3 "" H 3300 2850 60 0000 C CNN + 1 3300 2850 + 1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6947F8E1 +P 3400 2300 +F 0 "D2" H 3400 2400 50 0000 C CNN +F 1 "eSim_Diode" H 3400 2200 50 0000 C CNN +F 2 "" H 3400 2300 60 0000 C CNN +F 3 "" H 3400 2300 60 0000 C CNN + 1 3400 2300 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 6947F8E2 +P 3400 4500 +F 0 "U3" H 3350 4400 60 0000 C CNN +F 1 "zener" H 3400 4600 60 0000 C CNN +F 2 "" H 3450 4500 60 0000 C CNN +F 3 "" H 3450 4500 60 0000 C CNN + 1 3400 4500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6947F8E3 +P 3800 2500 +F 0 "Q2" H 3700 2550 50 0000 R CNN +F 1 "eSim_PNP" H 3750 2650 50 0000 R CNN +F 2 "" H 4000 2600 29 0000 C CNN +F 3 "" H 3800 2500 60 0000 C CNN + 1 3800 2500 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6947F8E4 +P 3800 3650 +F 0 "Q3" H 3700 3700 50 0000 R CNN +F 1 "eSim_NPN" H 3750 3800 50 0000 R CNN +F 2 "" H 4000 3750 29 0000 C CNN +F 3 "" H 3800 3650 60 0000 C CNN + 1 3800 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 6947F8E5 +P 3850 4050 +F 0 "R2" H 3900 4180 50 0000 C CNN +F 1 "4k" H 3900 4000 50 0000 C CNN +F 2 "" H 3900 4030 30 0000 C CNN +F 3 "" V 3900 4100 30 0000 C CNN + 1 3850 4050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 6947F8E6 +P 3850 4550 +F 0 "R3" H 3900 4680 50 0000 C CNN +F 1 "1.5k" H 3900 4500 50 0000 C CNN +F 2 "" H 3900 4530 30 0000 C CNN +F 3 "" V 3900 4600 30 0000 C CNN + 1 3850 4550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6947F8E7 +P 3900 5000 +F 0 "D3" H 3900 5100 50 0000 C CNN +F 1 "eSim_Diode" H 3900 4900 50 0000 C CNN +F 2 "" H 3900 5000 60 0000 C CNN +F 3 "" H 3900 5000 60 0000 C CNN + 1 3900 5000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6947F8E8 +P 4300 4350 +F 0 "Q4" H 4200 4400 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4500 50 0000 R CNN +F 2 "" H 4500 4450 29 0000 C CNN +F 3 "" H 4300 4350 60 0000 C CNN + 1 4300 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6947F8E9 +P 4500 2500 +F 0 "Q5" H 4400 2550 50 0000 R CNN +F 1 "eSim_PNP" H 4450 2650 50 0000 R CNN +F 2 "" H 4700 2600 29 0000 C CNN +F 3 "" H 4500 2500 60 0000 C CNN + 1 4500 2500 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6947F8EA +P 4800 2200 +F 0 "D4" H 4800 2300 50 0000 C CNN +F 1 "eSim_Diode" H 4800 2100 50 0000 C CNN +F 2 "" H 4800 2200 60 0000 C CNN +F 3 "" H 4800 2200 60 0000 C CNN + 1 4800 2200 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6947F8EB +P 4700 3150 +F 0 "Q7" H 4600 3200 50 0000 R CNN +F 1 "eSim_PNP" H 4650 3300 50 0000 R CNN +F 2 "" H 4900 3250 29 0000 C CNN +F 3 "" H 4700 3150 60 0000 C CNN + 1 4700 3150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 6947F8EC +P 4900 4350 +F 0 "Q8" H 4800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 4850 4500 50 0000 R CNN +F 2 "" H 5100 4450 29 0000 C CNN +F 3 "" H 4900 4350 60 0000 C CNN + 1 4900 4350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 6947F8ED +P 4500 4850 +F 0 "Q6" H 4400 4900 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5000 50 0000 R CNN +F 2 "" H 4700 4950 29 0000 C CNN +F 3 "" H 4500 4850 60 0000 C CNN + 1 4500 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6947F8EE +P 5600 3500 +F 0 "Q10" H 5500 3550 50 0000 R CNN +F 1 "eSim_NPN" H 5550 3650 50 0000 R CNN +F 2 "" H 5800 3600 29 0000 C CNN +F 3 "" H 5600 3500 60 0000 C CNN + 1 5600 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6947F8EF +P 5450 4200 +F 0 "Q9" H 5350 4250 50 0000 R CNN +F 1 "eSim_NPN" H 5400 4350 50 0000 R CNN +F 2 "" H 5650 4300 29 0000 C CNN +F 3 "" H 5450 4200 60 0000 C CNN + 1 5450 4200 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2950 3100 2950 4050 +Wire Wire Line + 3000 3550 2950 3550 +Connection ~ 2950 3550 +Wire Wire Line + 3400 2450 3400 2650 +Wire Wire Line + 3400 2150 3400 2000 +Wire Wire Line + 2750 2000 6200 2000 +Wire Wire Line + 2950 2800 2950 2000 +Connection ~ 2950 2000 +Wire Wire Line + 3400 3050 3400 4200 +Wire Wire Line + 3400 3550 3300 3550 +Wire Wire Line + 3100 2850 3100 3150 +Connection ~ 3400 3550 +Wire Wire Line + 3900 2000 3900 2300 +Connection ~ 3400 2000 +Wire Wire Line + 3600 2500 3400 2500 +Connection ~ 3400 2500 +Wire Wire Line + 3900 2700 3900 3450 +Wire Wire Line + 3600 3650 3400 3650 +Connection ~ 3400 3650 +Wire Wire Line + 3100 3150 3900 3150 +Connection ~ 3900 3150 +Wire Wire Line + 3900 3800 3900 3950 +Wire Wire Line + 3900 4250 3900 4450 +Wire Wire Line + 3900 4750 3900 4850 +Wire Wire Line + 3900 5150 3900 5350 +Wire Wire Line + 2950 5350 4600 5350 +Wire Wire Line + 2950 5350 2950 4550 +Wire Wire Line + 3400 4700 3400 5350 +Connection ~ 3400 5350 +Wire Wire Line + 4400 2000 4400 2300 +Connection ~ 3900 2000 +Wire Wire Line + 4400 2700 4400 4150 +Wire Wire Line + 4100 4350 3900 4350 +Connection ~ 3900 4350 +Connection ~ 4400 2000 +Wire Wire Line + 4800 2000 4800 2050 +Wire Wire Line + 4800 2350 4800 2950 +Wire Wire Line + 4800 2500 4700 2500 +Connection ~ 4800 2500 +Wire Wire Line + 4500 3150 4400 3150 +Connection ~ 4400 3150 +Wire Wire Line + 4800 3350 4800 4150 +Wire Wire Line + 4400 4550 4400 4600 +Wire Wire Line + 4400 4600 4800 4600 +Wire Wire Line + 4800 4600 4800 4550 +Wire Wire Line + 3900 4800 4300 4800 +Wire Wire Line + 4300 4800 4300 4850 +Connection ~ 3900 4800 +Wire Wire Line + 4600 4650 4600 4600 +Connection ~ 4600 4600 +Wire Wire Line + 4600 5050 4600 5500 +Connection ~ 3900 5350 +Connection ~ 4600 5350 +Wire Wire Line + 4050 4350 4050 5500 +Connection ~ 4050 4350 +Wire Wire Line + 5100 4350 5200 4350 +Wire Wire Line + 5200 4350 5200 5500 +Wire Wire Line + 5400 3500 4800 3500 +Connection ~ 4800 3500 +Wire Wire Line + 5700 2000 5700 3300 +Connection ~ 4800 2000 +Wire Wire Line + 5200 3500 5200 3000 +Wire Wire Line + 5200 3000 6750 3000 +Connection ~ 5200 3500 +Wire Wire Line + 5350 4000 5350 3500 +Connection ~ 5350 3500 +Wire Wire Line + 5350 4400 5350 4850 +$Comp +L eSim_R R4 +U 1 1 6947F8F0 +P 5850 4250 +F 0 "R4" H 5900 4380 50 0000 C CNN +F 1 "1.5k" H 5900 4200 50 0000 C CNN +F 2 "" H 5900 4230 30 0000 C CNN +F 3 "" V 5900 4300 30 0000 C CNN + 1 5850 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5750 4200 5650 4200 +$Comp +L eSim_NPN Q11 +U 1 1 6947F8F1 +P 6100 3750 +F 0 "Q11" H 6000 3800 50 0000 R CNN +F 1 "eSim_NPN" H 6050 3900 50 0000 R CNN +F 2 "" H 6300 3850 29 0000 C CNN +F 3 "" H 6100 3750 60 0000 C CNN + 1 6100 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3700 5700 3750 +Wire Wire Line + 5700 3750 5900 3750 +Wire Wire Line + 6200 3950 6200 4200 +Wire Wire Line + 6050 4200 6750 4200 +$Comp +L eSim_R R5 +U 1 1 6947F8F2 +P 6150 2600 +F 0 "R5" H 6200 2730 50 0000 C CNN +F 1 "500" H 6200 2550 50 0000 C CNN +F 2 "" H 6200 2580 30 0000 C CNN +F 3 "" V 6200 2650 30 0000 C CNN + 1 6150 2600 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 2000 6200 2500 +Connection ~ 5700 2000 +Wire Wire Line + 6200 2800 6200 3550 +Wire Wire Line + 6200 3400 6750 3400 +Connection ~ 6200 3400 +Wire Wire Line + 6750 4200 6750 4150 +Connection ~ 6200 4200 +$Comp +L PORT U1 +U 1 1 6947F926 +P 7000 4150 +F 0 "U1" H 7050 4250 30 0000 C CNN +F 1 "PORT" H 7000 4150 30 0000 C CNN +F 2 "" H 7000 4150 60 0000 C CNN +F 3 "" H 7000 4150 60 0000 C CNN + 1 7000 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6947F9FB +P 7000 3400 +F 0 "U1" H 7050 3500 30 0000 C CNN +F 1 "PORT" H 7000 3400 30 0000 C CNN +F 2 "" H 7000 3400 60 0000 C CNN +F 3 "" H 7000 3400 60 0000 C CNN + 2 7000 3400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6947FA53 +P 2500 2000 +F 0 "U1" H 2550 2100 30 0000 C CNN +F 1 "PORT" H 2500 2000 30 0000 C CNN +F 2 "" H 2500 2000 60 0000 C CNN +F 3 "" H 2500 2000 60 0000 C CNN + 3 2500 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6947FA59 +P 4350 5500 +F 0 "U1" H 4400 5600 30 0000 C CNN +F 1 "PORT" H 4350 5500 30 0000 C CNN +F 2 "" H 4350 5500 60 0000 C CNN +F 3 "" H 4350 5500 60 0000 C CNN + 4 4350 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6947FB17 +P 3800 5500 +F 0 "U1" H 3850 5600 30 0000 C CNN +F 1 "PORT" H 3800 5500 30 0000 C CNN +F 2 "" H 3800 5500 60 0000 C CNN +F 3 "" H 3800 5500 60 0000 C CNN + 5 3800 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6947FB1D +P 4950 5500 +F 0 "U1" H 5000 5600 30 0000 C CNN +F 1 "PORT" H 4950 5500 30 0000 C CNN +F 2 "" H 4950 5500 60 0000 C CNN +F 3 "" H 4950 5500 60 0000 C CNN + 6 4950 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6947FB23 +P 7000 3000 +F 0 "U1" H 7050 3100 30 0000 C CNN +F 1 "PORT" H 7000 3000 30 0000 C CNN +F 2 "" H 7000 3000 60 0000 C CNN +F 3 "" H 7000 3000 60 0000 C CNN + 7 7000 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6947FB29 +P 5350 5100 +F 0 "U1" H 5400 5200 30 0000 C CNN +F 1 "PORT" H 5350 5100 30 0000 C CNN +F 2 "" H 5350 5100 60 0000 C CNN +F 3 "" H 5350 5100 60 0000 C CNN + 8 5350 5100 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CA3085/CA3085.sub b/library/SubcircuitLibrary/CA3085/CA3085.sub new file mode 100644 index 000000000..716cf96df --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085.sub @@ -0,0 +1,37 @@ +* Subcircuit CA3085 +.subckt CA3085 net-_q11-pad3_ net-_q11-pad1_ net-_d2-pad1_ net-_d3-pad2_ net-_q4-pad2_ net-_q8-pad2_ net-_q10-pad2_ net-_q9-pad3_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ca3085\ca3085.cir +.include D.lib +.include PNP.lib +.include NPN.lib +r1 net-_d2-pad1_ net-_d1-pad1_ 40k +* u2 net-_d3-pad2_ net-_d1-pad1_ zener +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_d1-pad2_ net-_q1-pad2_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +* u3 net-_d3-pad2_ net-_d1-pad2_ zener +q2 net-_q1-pad2_ net-_d2-pad2_ net-_d2-pad1_ Q2N2907A +q3 net-_q1-pad2_ net-_d1-pad2_ ? Q2N2222 +r2 ? net-_q4-pad2_ 4k +r3 net-_q4-pad2_ net-_d3-pad1_ 1.5k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q4-pad1_ net-_d4-pad2_ net-_d2-pad1_ Q2N2907A +d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148 +q7 net-_q10-pad2_ net-_q4-pad1_ net-_d4-pad2_ Q2N2907A +q8 net-_q10-pad2_ net-_q8-pad2_ net-_q4-pad3_ Q2N2222 +q6 net-_q4-pad3_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +q10 net-_d2-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q9 net-_q10-pad2_ net-_q9-pad2_ net-_q9-pad3_ Q2N2222 +r4 net-_q9-pad2_ net-_q11-pad3_ 1.5k +q11 net-_q11-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r5 net-_d2-pad1_ net-_q11-pad1_ 500 +a1 net-_d3-pad2_ net-_d1-pad1_ u2 +a2 net-_d3-pad2_ net-_d1-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends CA3085 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3085/CA3085_Previous_Values.xml b/library/SubcircuitLibrary/CA3085/CA3085_Previous_Values.xml new file mode 100644 index 000000000..625f7ce0a --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/CA3085_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3085/D.lib b/library/SubcircuitLibrary/CA3085/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/CA3085/NPN.lib b/library/SubcircuitLibrary/CA3085/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/CA3085/PNP.lib b/library/SubcircuitLibrary/CA3085/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/CA3085/analysis b/library/SubcircuitLibrary/CA3085/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CA3085/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub-cache.lib b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub-cache.lib new file mode 100644 index 000000000..27b0f7f2a --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir new file mode 100644 index 000000000..adc5ca880 --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir @@ -0,0 +1,25 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\IC74180_sub\IC74180_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 10/21/25 12:46:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad3_ d_xnor +U3 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U3-Pad3_ d_xnor +U4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U4-Pad3_ d_xnor +U5 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_xnor +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_xor +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_xor +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_xnor +U9 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad3_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad5_ d_nor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U1-Pad6_ d_nor + +.end diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir.out b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir.out new file mode 100644 index 000000000..2f2a94b14 --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.cir.out @@ -0,0 +1,68 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ic74180_sub\ic74180_sub.cir + +* u2 net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.pro b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sch b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sch new file mode 100644 index 000000000..3d6b2aba3 --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sch @@ -0,0 +1,483 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:IC74180_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xnor U2 +U 1 1 68F24341 +P 2350 2700 +F 0 "U2" H 2350 2700 60 0000 C CNN +F 1 "d_xnor" H 2400 2800 47 0000 C CNN +F 2 "" H 2350 2700 60 0000 C CNN +F 3 "" H 2350 2700 60 0000 C CNN + 1 2350 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U3 +U 1 1 68F24342 +P 2350 3450 +F 0 "U3" H 2350 3450 60 0000 C CNN +F 1 "d_xnor" H 2400 3550 47 0000 C CNN +F 2 "" H 2350 3450 60 0000 C CNN +F 3 "" H 2350 3450 60 0000 C CNN + 1 2350 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U4 +U 1 1 68F24343 +P 2350 4350 +F 0 "U4" H 2350 4350 60 0000 C CNN +F 1 "d_xnor" H 2400 4450 47 0000 C CNN +F 2 "" H 2350 4350 60 0000 C CNN +F 3 "" H 2350 4350 60 0000 C CNN + 1 2350 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U5 +U 1 1 68F24344 +P 2350 5100 +F 0 "U5" H 2350 5100 60 0000 C CNN +F 1 "d_xnor" H 2400 5200 47 0000 C CNN +F 2 "" H 2350 5100 60 0000 C CNN +F 3 "" H 2350 5100 60 0000 C CNN + 1 2350 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 68F24345 +P 3600 4700 +F 0 "U7" H 3600 4700 60 0000 C CNN +F 1 "d_xor" H 3650 4800 47 0000 C CNN +F 2 "" H 3600 4700 60 0000 C CNN +F 3 "" H 3600 4700 60 0000 C CNN + 1 3600 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 68F24346 +P 3600 3050 +F 0 "U6" H 3600 3050 60 0000 C CNN +F 1 "d_xor" H 3650 3150 47 0000 C CNN +F 2 "" H 3600 3050 60 0000 C CNN +F 3 "" H 3600 3050 60 0000 C CNN + 1 3600 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U8 +U 1 1 68F24347 +P 4750 3850 +F 0 "U8" H 4750 3850 60 0000 C CNN +F 1 "d_xnor" H 4800 3950 47 0000 C CNN +F 2 "" H 4750 3850 60 0000 C CNN +F 3 "" H 4750 3850 60 0000 C CNN + 1 4750 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68F24348 +P 5850 3800 +F 0 "U9" H 5850 3700 60 0000 C CNN +F 1 "d_inverter" H 5850 3950 60 0000 C CNN +F 2 "" H 5900 3750 60 0000 C CNN +F 3 "" H 5900 3750 60 0000 C CNN + 1 5850 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 68F24349 +P 7500 2750 +F 0 "U10" H 7500 2750 60 0000 C CNN +F 1 "d_and" H 7550 2850 60 0000 C CNN +F 2 "" H 7500 2750 60 0000 C CNN +F 3 "" H 7500 2750 60 0000 C CNN + 1 7500 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 68F2434A +P 7500 3350 +F 0 "U11" H 7500 3350 60 0000 C CNN +F 1 "d_and" H 7550 3450 60 0000 C CNN +F 2 "" H 7500 3350 60 0000 C CNN +F 3 "" H 7500 3350 60 0000 C CNN + 1 7500 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 68F2434B +P 7500 4350 +F 0 "U12" H 7500 4350 60 0000 C CNN +F 1 "d_and" H 7550 4450 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7500 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 68F2434C +P 7500 4950 +F 0 "U13" H 7500 4950 60 0000 C CNN +F 1 "d_and" H 7550 5050 60 0000 C CNN +F 2 "" H 7500 4950 60 0000 C CNN +F 3 "" H 7500 4950 60 0000 C CNN + 1 7500 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2650 2950 2650 +Wire Wire Line + 2950 2650 2950 2950 +Wire Wire Line + 2950 2950 3150 2950 +Wire Wire Line + 3150 3050 2950 3050 +Wire Wire Line + 2950 3050 2950 3400 +Wire Wire Line + 2950 3400 2800 3400 +Wire Wire Line + 2800 4300 2950 4300 +Wire Wire Line + 2950 4300 2950 4600 +Wire Wire Line + 2950 4600 3150 4600 +Wire Wire Line + 3150 4700 2950 4700 +Wire Wire Line + 2950 4700 2950 5050 +Wire Wire Line + 2950 5050 2800 5050 +Wire Wire Line + 4050 3000 4150 3000 +Wire Wire Line + 4150 3000 4150 3750 +Wire Wire Line + 4150 3750 4300 3750 +Wire Wire Line + 4300 3850 4150 3850 +Wire Wire Line + 4150 3850 4150 4650 +Wire Wire Line + 4150 4650 4050 4650 +Wire Wire Line + 5200 3800 5550 3800 +Wire Wire Line + 7050 2650 5400 2650 +Wire Wire Line + 5400 2650 5400 4350 +Wire Wire Line + 5400 4350 7050 4350 +Wire Wire Line + 7050 2750 6300 2750 +Wire Wire Line + 6300 2750 6300 5350 +Wire Wire Line + 6300 5350 1900 5350 +Connection ~ 5400 3800 +Wire Wire Line + 7050 3250 6550 3250 +Wire Wire Line + 6550 3250 6550 4850 +Wire Wire Line + 6550 4850 7050 4850 +Wire Wire Line + 6150 3800 6550 3800 +Connection ~ 6550 3800 +Wire Wire Line + 7050 3350 6750 3350 +Wire Wire Line + 6750 3350 6750 5700 +Wire Wire Line + 6750 5700 1900 5700 +Wire Wire Line + 7950 2700 8200 2700 +Wire Wire Line + 8200 2700 8200 2950 +Wire Wire Line + 8200 2950 8600 2950 +Wire Wire Line + 8200 3050 8600 3050 +Wire Wire Line + 8200 3050 8200 3300 +Wire Wire Line + 8200 3300 7950 3300 +Wire Wire Line + 7950 4300 8200 4300 +Wire Wire Line + 8200 4300 8200 4550 +Wire Wire Line + 8200 4550 8600 4550 +Wire Wire Line + 8200 4650 8600 4650 +Wire Wire Line + 8200 4650 8200 4900 +Wire Wire Line + 8200 4900 7950 4900 +Wire Wire Line + 7050 4250 6750 4250 +Connection ~ 6750 4250 +Wire Wire Line + 7050 4950 6300 4950 +Connection ~ 6300 4950 +Wire Wire Line + 1800 5000 1900 5000 +Wire Wire Line + 1800 4250 1900 4250 +Wire Wire Line + 1800 3350 1900 3350 +Wire Wire Line + 1800 2600 1900 2600 +Wire Wire Line + 9850 3000 10550 3000 +Wire Wire Line + 9900 4600 10550 4600 +$Comp +L PORT U1 +U 8 1 68F24372 +P 1150 2700 +F 0 "U1" H 1200 2800 30 0000 C CNN +F 1 "PORT" H 1150 2700 30 0000 C CNN +F 2 "" H 1150 2700 60 0000 C CNN +F 3 "" H 1150 2700 60 0000 C CNN + 8 1150 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68F24439 +P 1650 5700 +F 0 "U1" H 1700 5800 30 0000 C CNN +F 1 "PORT" H 1650 5700 30 0000 C CNN +F 2 "" H 1650 5700 60 0000 C CNN +F 3 "" H 1650 5700 60 0000 C CNN + 3 1650 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68F24514 +P 1550 3350 +F 0 "U1" H 1600 3450 30 0000 C CNN +F 1 "PORT" H 1550 3350 30 0000 C CNN +F 2 "" H 1550 3350 60 0000 C CNN +F 3 "" H 1550 3350 60 0000 C CNN + 9 1550 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68F245C9 +P 1150 3450 +F 0 "U1" H 1200 3550 30 0000 C CNN +F 1 "PORT" H 1150 3450 30 0000 C CNN +F 2 "" H 1150 3450 60 0000 C CNN +F 3 "" H 1150 3450 60 0000 C CNN + 10 1150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68F246C0 +P 1550 4250 +F 0 "U1" H 1600 4350 30 0000 C CNN +F 1 "PORT" H 1550 4250 30 0000 C CNN +F 2 "" H 1550 4250 60 0000 C CNN +F 3 "" H 1550 4250 60 0000 C CNN + 11 1550 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68F2477B +P 1200 4350 +F 0 "U1" H 1250 4450 30 0000 C CNN +F 1 "PORT" H 1200 4350 30 0000 C CNN +F 2 "" H 1200 4350 60 0000 C CNN +F 3 "" H 1200 4350 60 0000 C CNN + 12 1200 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68F2487C +P 10800 3000 +F 0 "U1" H 10850 3100 30 0000 C CNN +F 1 "PORT" H 10800 3000 30 0000 C CNN +F 2 "" H 10800 3000 60 0000 C CNN +F 3 "" H 10800 3000 60 0000 C CNN + 5 10800 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 68F2493B +P 1550 5000 +F 0 "U1" H 1600 5100 30 0000 C CNN +F 1 "PORT" H 1550 5000 30 0000 C CNN +F 2 "" H 1550 5000 60 0000 C CNN +F 3 "" H 1550 5000 60 0000 C CNN + 1 1550 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68F24A38 +P 10800 4600 +F 0 "U1" H 10850 4700 30 0000 C CNN +F 1 "PORT" H 10800 4600 30 0000 C CNN +F 2 "" H 10800 4600 60 0000 C CNN +F 3 "" H 10800 4600 60 0000 C CNN + 6 10800 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68F24AE0 +P 1150 5100 +F 0 "U1" H 1200 5200 30 0000 C CNN +F 1 "PORT" H 1150 5100 30 0000 C CNN +F 2 "" H 1150 5100 60 0000 C CNN +F 3 "" H 1150 5100 60 0000 C CNN + 2 1150 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68F24B7F +P 1550 2600 +F 0 "U1" H 1600 2700 30 0000 C CNN +F 1 "PORT" H 1550 2600 30 0000 C CNN +F 2 "" H 1550 2600 60 0000 C CNN +F 3 "" H 1550 2600 60 0000 C CNN + 7 1550 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68F24C12 +P 1650 5350 +F 0 "U1" H 1700 5450 30 0000 C CNN +F 1 "PORT" H 1650 5350 30 0000 C CNN +F 2 "" H 1650 5350 60 0000 C CNN +F 3 "" H 1650 5350 60 0000 C CNN + 4 1650 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 5100 1400 5100 +Wire Wire Line + 1900 4350 1450 4350 +Wire Wire Line + 1900 3450 1400 3450 +Wire Wire Line + 1900 2700 1400 2700 +Wire Wire Line + 8600 2950 8600 2900 +Wire Wire Line + 8600 2900 8950 2900 +Wire Wire Line + 8600 3050 8600 3100 +Wire Wire Line + 8600 3100 8950 3100 +Wire Wire Line + 8600 4550 8600 4500 +Wire Wire Line + 8600 4500 9000 4500 +Wire Wire Line + 8600 4700 9000 4700 +Wire Wire Line + 8600 4650 8600 4700 +$Comp +L d_nor U14 +U 1 1 68F72F45 +P 9400 3050 +F 0 "U14" H 9400 3050 60 0000 C CNN +F 1 "d_nor" H 9450 3150 60 0000 C CNN +F 2 "" H 9400 3050 60 0000 C CNN +F 3 "" H 9400 3050 60 0000 C CNN + 1 9400 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 68F73052 +P 9450 4650 +F 0 "U15" H 9450 4650 60 0000 C CNN +F 1 "d_nor" H 9500 4750 60 0000 C CNN +F 2 "" H 9450 4650 60 0000 C CNN +F 3 "" H 9450 4650 60 0000 C CNN + 1 9450 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 2900 8950 2950 +Wire Wire Line + 8950 3100 8950 3050 +Wire Wire Line + 9000 4500 9000 4550 +Wire Wire Line + 9000 4700 9000 4650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sub b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sub new file mode 100644 index 000000000..5ed2e3a0d --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub.sub @@ -0,0 +1,62 @@ +* Subcircuit IC74180_sub +.subckt IC74180_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\ic74180_sub\ic74180_sub.cir +* u2 net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC74180_sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC74180_sub/IC74180_sub_Previous_Values.xml b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub_Previous_Values.xml new file mode 100644 index 000000000..1ceff4cfa --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/IC74180_sub_Previous_Values.xml @@ -0,0 +1 @@ +d_xnord_xnord_xnord_xnord_xord_xord_xnord_inverterd_andd_andd_andd_andd_andd_andd_nord_nortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC74180_sub/analysis b/library/SubcircuitLibrary/IC74180_sub/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC74180_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM161/D.lib b/library/SubcircuitLibrary/LM161/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LM161/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM161/LM161-cache.lib b/library/SubcircuitLibrary/LM161/LM161-cache.lib new file mode 100644 index 000000000..bfc9a8eb0 --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161-cache.lib @@ -0,0 +1,137 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM161/LM161.cir b/library/SubcircuitLibrary/LM161/LM161.cir new file mode 100644 index 000000000..4a539f0eb --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161.cir @@ -0,0 +1,72 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\LM161\LM161.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 11/29/25 18:37:37 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q3 Net-_Q3-Pad1_ Net-_D1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +R4 Net-_Q3-Pad1_ Net-_D1-Pad1_ 9k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_Diode +R3 Net-_Q3-Pad3_ Net-_Q4-Pad1_ 1450 +U2 GND Net-_D3-Pad2_ zener +Q5 Net-_Q3-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R1 Net-_Q3-Pad3_ Net-_Q1-Pad1_ 1450 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +R2 Net-_Q2-Pad3_ Net-_Q11-Pad3_ 400 +U3 Net-_Q13-Pad2_ Net-_Q5-Pad3_ zener +Q6 Net-_Q13-Pad2_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_NPN +U4 Net-_Q8-Pad1_ Net-_Q7-Pad3_ zener +Q8 Net-_Q8-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ GND eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ GND eSim_NPN +Q13 Net-_Q12-Pad2_ Net-_Q13-Pad2_ Net-_Q11-Pad1_ eSim_NPN +R6 Net-_Q10-Pad1_ Net-_Q10-Pad2_ 1.3k +R8 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.3k +R5 Net-_Q28-Pad1_ Net-_Q10-Pad1_ 1k +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R7 Net-_Q28-Pad1_ Net-_Q12-Pad1_ 1k +Q9 Net-_Q10-Pad2_ Net-_Q8-Pad1_ Net-_Q11-Pad1_ eSim_NPN +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q15 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_D5-Pad2_ eSim_NPN +Q17 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q17-Pad3_ eSim_NPN +R9 Net-_Q28-Pad1_ Net-_Q14-Pad2_ 4k +R11 Net-_Q28-Pad1_ Net-_Q17-Pad3_ 1.4k +Q19 Net-_Q17-Pad3_ Net-_Q14-Pad1_ Net-_Q19-Pad3_ eSim_NPN +Q21 Net-_Q17-Pad3_ Net-_Q14-Pad1_ Net-_D4-Pad1_ eSim_NPN +R12 Net-_Q19-Pad3_ Net-_Q24-Pad2_ 235 +R13 Net-_Q24-Pad2_ GND 800 +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q24 Net-_D4-Pad2_ Net-_Q24-Pad2_ GND eSim_NPN +Q23 Net-_Q23-Pad1_ Net-_Q17-Pad3_ Net-_D4-Pad1_ eSim_NPN +R14 Net-_Q28-Pad1_ Net-_Q23-Pad1_ 100 +D6 GND Net-_D6-Pad2_ eSim_Diode +D5 GND Net-_D5-Pad2_ eSim_Diode +Q16 Net-_Q16-Pad1_ Net-_Q16-Pad2_ Net-_Q12-Pad1_ eSim_NPN +Q18 Net-_Q16-Pad1_ Net-_Q16-Pad2_ Net-_D6-Pad2_ eSim_NPN +Q20 Net-_Q16-Pad1_ Net-_Q16-Pad2_ Net-_Q20-Pad3_ eSim_NPN +R10 Net-_Q28-Pad1_ Net-_Q16-Pad2_ 1k +R15 Net-_Q28-Pad1_ Net-_Q20-Pad3_ 1.4k +Q22 Net-_Q20-Pad3_ Net-_Q16-Pad1_ Net-_Q22-Pad3_ eSim_NPN +Q25 Net-_Q20-Pad3_ Net-_Q16-Pad1_ Net-_D7-Pad1_ eSim_NPN +R17 Net-_Q27-Pad2_ Net-_Q22-Pad3_ 235 +D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode +Q27 Net-_D7-Pad2_ Net-_Q27-Pad2_ GND eSim_NPN +R16 Net-_Q27-Pad2_ GND 800 +Q26 Net-_Q26-Pad1_ Net-_Q20-Pad3_ Net-_D7-Pad1_ eSim_NPN +R18 Net-_Q28-Pad1_ Net-_Q26-Pad1_ 100 +Q28 Net-_Q28-Pad1_ Net-_Q28-Pad2_ Net-_Q28-Pad3_ eSim_NPN +R21 Net-_Q28-Pad1_ Net-_Q28-Pad2_ 5k +R19 Net-_Q28-Pad3_ Net-_Q2-Pad2_ 3.2k +U5 Net-_Q11-Pad3_ Net-_Q28-Pad2_ zener +R20 Net-_Q2-Pad2_ Net-_Q11-Pad2_ 387 +Q29 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +U1 Net-_Q3-Pad1_ ? Net-_Q1-Pad2_ Net-_Q4-Pad2_ ? Net-_Q11-Pad3_ ? Net-_D6-Pad2_ Net-_D7-Pad2_ GND Net-_D4-Pad2_ ? Net-_D5-Pad2_ Net-_Q28-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM161/LM161.cir.out b/library/SubcircuitLibrary/LM161/LM161.cir.out new file mode 100644 index 000000000..1c85d4919 --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161.cir.out @@ -0,0 +1,87 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\lm161\lm161.cir + +.include NPN.lib +.include D.lib +q3 net-_q3-pad1_ net-_d1-pad1_ net-_q3-pad3_ Q2N2222 +r4 net-_q3-pad1_ net-_d1-pad1_ 9k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148 +r3 net-_q3-pad3_ net-_q4-pad1_ 1450 +* u2 gnd net-_d3-pad2_ zener +q5 net-_q3-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q1-pad1_ 1450 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +r2 net-_q2-pad3_ net-_q11-pad3_ 400 +* u3 net-_q13-pad2_ net-_q5-pad3_ zener +q6 net-_q13-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_q3-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2222 +* u4 net-_q8-pad1_ net-_q7-pad3_ zener +q8 net-_q8-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ gnd Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ gnd Q2N2222 +q13 net-_q12-pad2_ net-_q13-pad2_ net-_q11-pad1_ Q2N2222 +r6 net-_q10-pad1_ net-_q10-pad2_ 1.3k +r8 net-_q12-pad1_ net-_q12-pad2_ 1.3k +r5 net-_q28-pad1_ net-_q10-pad1_ 1k +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r7 net-_q28-pad1_ net-_q12-pad1_ 1k +q9 net-_q10-pad2_ net-_q8-pad1_ net-_q11-pad1_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2222 +q15 net-_q14-pad1_ net-_q14-pad2_ net-_d5-pad2_ Q2N2222 +q17 net-_q14-pad1_ net-_q14-pad2_ net-_q17-pad3_ Q2N2222 +r9 net-_q28-pad1_ net-_q14-pad2_ 4k +r11 net-_q28-pad1_ net-_q17-pad3_ 1.4k +q19 net-_q17-pad3_ net-_q14-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q17-pad3_ net-_q14-pad1_ net-_d4-pad1_ Q2N2222 +r12 net-_q19-pad3_ net-_q24-pad2_ 235 +r13 net-_q24-pad2_ gnd 800 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q24 net-_d4-pad2_ net-_q24-pad2_ gnd Q2N2222 +q23 net-_q23-pad1_ net-_q17-pad3_ net-_d4-pad1_ Q2N2222 +r14 net-_q28-pad1_ net-_q23-pad1_ 100 +d6 gnd net-_d6-pad2_ 1N4148 +d5 gnd net-_d5-pad2_ 1N4148 +q16 net-_q16-pad1_ net-_q16-pad2_ net-_q12-pad1_ Q2N2222 +q18 net-_q16-pad1_ net-_q16-pad2_ net-_d6-pad2_ Q2N2222 +q20 net-_q16-pad1_ net-_q16-pad2_ net-_q20-pad3_ Q2N2222 +r10 net-_q28-pad1_ net-_q16-pad2_ 1k +r15 net-_q28-pad1_ net-_q20-pad3_ 1.4k +q22 net-_q20-pad3_ net-_q16-pad1_ net-_q22-pad3_ Q2N2222 +q25 net-_q20-pad3_ net-_q16-pad1_ net-_d7-pad1_ Q2N2222 +r17 net-_q27-pad2_ net-_q22-pad3_ 235 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +q27 net-_d7-pad2_ net-_q27-pad2_ gnd Q2N2222 +r16 net-_q27-pad2_ gnd 800 +q26 net-_q26-pad1_ net-_q20-pad3_ net-_d7-pad1_ Q2N2222 +r18 net-_q28-pad1_ net-_q26-pad1_ 100 +q28 net-_q28-pad1_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r21 net-_q28-pad1_ net-_q28-pad2_ 5k +r19 net-_q28-pad3_ net-_q2-pad2_ 3.2k +* u5 net-_q11-pad3_ net-_q28-pad2_ zener +r20 net-_q2-pad2_ net-_q11-pad2_ 387 +q29 net-_q11-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +* u1 net-_q3-pad1_ ? net-_q1-pad2_ net-_q4-pad2_ ? net-_q11-pad3_ ? net-_d6-pad2_ net-_d7-pad2_ gnd net-_d4-pad2_ ? net-_d5-pad2_ net-_q28-pad1_ port +a1 gnd net-_d3-pad2_ u2 +a2 net-_q13-pad2_ net-_q5-pad3_ u3 +a3 net-_q8-pad1_ net-_q7-pad3_ u4 +a4 net-_q11-pad3_ net-_q28-pad2_ u5 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM161/LM161.pro b/library/SubcircuitLibrary/LM161/LM161.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM161/LM161.sch b/library/SubcircuitLibrary/LM161/LM161.sch new file mode 100644 index 000000000..3759d9b1b --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161.sch @@ -0,0 +1,1344 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM161-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q3 +U 1 1 692461A3 +P 3550 2300 +F 0 "Q3" H 3450 2350 50 0000 R CNN +F 1 "eSim_NPN" H 3500 2450 50 0000 R CNN +F 2 "" H 3750 2400 29 0000 C CNN +F 3 "" H 3550 2300 60 0000 C CNN + 1 3550 2300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 692461A4 +P 3750 1900 +F 0 "R4" H 3800 2030 50 0000 C CNN +F 1 "9k" H 3800 1850 50 0000 C CNN +F 2 "" H 3800 1880 30 0000 C CNN +F 3 "" V 3800 1950 30 0000 C CNN + 1 3750 1900 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 692461A5 +P 3800 2550 +F 0 "D1" H 3800 2650 50 0000 C CNN +F 1 "eSim_Diode" H 3800 2450 50 0000 C CNN +F 2 "" H 3800 2550 60 0000 C CNN +F 3 "" H 3800 2550 60 0000 C CNN + 1 3800 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 692461A6 +P 3800 2900 +F 0 "D2" H 3800 3000 50 0000 C CNN +F 1 "eSim_Diode" H 3800 2800 50 0000 C CNN +F 2 "" H 3800 2900 60 0000 C CNN +F 3 "" H 3800 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~ 8750 4500 +Wire Wire Line + 9350 4500 9350 4800 +Connection ~ 9000 4500 +$Comp +L eSim_R R21 +U 1 1 692461DF +P 9300 4900 +F 0 "R21" H 9350 5030 50 0000 C CNN +F 1 "5k" H 9350 4850 50 0000 C CNN +F 2 "" H 9350 4880 30 0000 C CNN +F 3 "" V 9350 4950 30 0000 C CNN + 1 9300 4900 + 0 1 1 0 +$EndComp +Wire Wire Line + 9350 5100 9350 7100 +Wire Wire Line + 9350 6750 9300 6750 +$Comp +L eSim_R R19 +U 1 1 692461E0 +P 8950 7100 +F 0 "R19" H 9000 7230 50 0000 C CNN +F 1 "3.2k" H 9000 7050 50 0000 C CNN +F 2 "" H 9000 7080 30 0000 C CNN +F 3 "" V 9000 7150 30 0000 C CNN + 1 8950 7100 + 0 1 1 0 +$EndComp +Wire Wire Line + 9000 6950 9000 7000 +$Comp +L zener U5 +U 1 1 692461E1 +P 9350 7400 +F 0 "U5" H 9300 7300 60 0000 C CNN +F 1 "zener" H 9350 7500 60 0000 C CNN +F 2 "" H 9400 7400 60 0000 C CNN +F 3 "" H 9400 7400 60 0000 C CNN + 1 9350 7400 + 0 -1 -1 0 +$EndComp +Connection ~ 9350 6750 +Wire Wire Line + 3600 6000 7900 6000 +Wire Wire Line + 7900 6000 7900 7400 +Wire Wire Line + 7900 7400 9000 7400 +Wire Wire Line + 9000 7300 9000 7450 +$Comp +L eSim_R R20 +U 1 1 692461E2 +P 8950 7550 +F 0 "R20" H 9000 7680 50 0000 C CNN +F 1 "387" H 9000 7500 50 0000 C CNN +F 2 "" H 9000 7530 30 0000 C CNN +F 3 "" V 9000 7600 30 0000 C CNN + 1 8950 7550 + 0 1 1 0 +$EndComp +Connection ~ 9000 7400 +$Comp +L eSim_NPN Q29 +U 1 1 692461E3 +P 9100 8100 +F 0 "Q29" H 9000 8150 50 0000 R CNN +F 1 "eSim_NPN" H 9050 8250 50 0000 R CNN +F 2 "" H 9300 8200 29 0000 C CNN +F 3 "" H 9100 8100 60 0000 C CNN + 1 9100 8100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 9000 7750 9000 7900 +Wire Wire Line + 9000 7850 9300 7850 +Wire Wire Line + 9300 7850 9300 8100 +Connection ~ 9000 7850 +Wire Wire Line + 7000 6950 7000 8400 +Wire Wire Line + 7000 8400 9350 8400 +Wire Wire Line + 9000 8400 9000 8300 +Connection ~ 5550 6950 +Wire Wire Line + 9350 8400 9350 7600 +Connection ~ 9000 8400 +Wire Wire Line + 9300 8000 7650 8000 +Wire Wire Line + 7650 8000 7650 6450 +Wire Wire Line + 7650 6450 4400 6450 +Wire Wire Line + 4400 6450 4400 6500 +Connection ~ 9300 8000 +Wire Wire Line + 5850 6500 5850 6450 +Connection ~ 5850 6450 +Wire Wire Line + 4850 6500 4850 6450 +Connection ~ 4850 6450 +$Comp +L PORT U1 +U 2 1 692483FE +P 1050 1500 +F 0 "U1" H 1100 1600 30 0000 C CNN +F 1 "PORT" H 1050 1500 30 0000 C CNN +F 2 "" H 1050 1500 60 0000 C CNN +F 3 "" H 1050 1500 60 0000 C CNN + 2 1050 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6924854B +P 2350 5000 +F 0 "U1" H 2400 5100 30 0000 C CNN +F 1 "PORT" H 2350 5000 30 0000 C CNN +F 2 "" H 2350 5000 60 0000 C CNN +F 3 "" H 2350 5000 60 0000 C CNN + 3 2350 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6924862C +P 2350 5350 +F 0 "U1" H 2400 5450 30 0000 C CNN +F 1 "PORT" H 2350 5350 30 0000 C CNN +F 2 "" H 2350 5350 60 0000 C CNN +F 3 "" H 2350 5350 60 0000 C CNN + 4 2350 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 692486F1 +P 1050 1800 +F 0 "U1" H 1100 1900 30 0000 C CNN +F 1 "PORT" H 1050 1800 30 0000 C CNN +F 2 "" H 1050 1800 60 0000 C CNN +F 3 "" H 1050 1800 60 0000 C CNN + 5 1050 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 692487AE +P 2550 6950 +F 0 "U1" H 2600 7050 30 0000 C CNN +F 1 "PORT" H 2550 6950 30 0000 C CNN +F 2 "" H 2550 6950 60 0000 C CNN +F 3 "" H 2550 6950 60 0000 C CNN + 6 2550 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 69248869 +P 1050 2050 +F 0 "U1" H 1100 2150 30 0000 C CNN +F 1 "PORT" H 1050 2050 30 0000 C CNN +F 2 "" H 1050 2050 60 0000 C CNN +F 3 "" H 1050 2050 60 0000 C CNN + 7 1050 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 69248938 +P 9700 4400 +F 0 "U1" H 9750 4500 30 0000 C CNN +F 1 "PORT" H 9700 4400 30 0000 C CNN +F 2 "" H 9700 4400 60 0000 C CNN +F 3 "" H 9700 4400 60 0000 C CNN + 8 9700 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 692489FD +P 9950 6450 +F 0 "U1" H 10000 6550 30 0000 C CNN +F 1 "PORT" H 9950 6450 30 0000 C CNN +F 2 "" H 9950 6450 60 0000 C CNN +F 3 "" H 9950 6450 60 0000 C CNN + 9 9950 6450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 69248AB2 +P 9700 4050 +F 0 "U1" H 9750 4150 30 0000 C CNN +F 1 "PORT" H 9700 4050 30 0000 C CNN +F 2 "" H 9700 4050 60 0000 C CNN +F 3 "" H 9700 4050 60 0000 C CNN + 10 9700 4050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 69248B87 +P 9700 3450 +F 0 "U1" H 9750 3550 30 0000 C CNN +F 1 "PORT" H 9700 3450 30 0000 C CNN +F 2 "" H 9700 3450 60 0000 C CNN +F 3 "" H 9700 3450 60 0000 C CNN + 11 9700 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 69248C5C +P 950 2300 +F 0 "U1" H 1000 2400 30 0000 C CNN +F 1 "PORT" H 950 2300 30 0000 C CNN +F 2 "" H 950 2300 60 0000 C CNN +F 3 "" H 950 2300 60 0000 C CNN + 12 950 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 69248D27 +P 9700 1550 +F 0 "U1" H 9750 1650 30 0000 C CNN +F 1 "PORT" H 9700 1550 30 0000 C CNN +F 2 "" H 9700 1550 60 0000 C CNN +F 3 "" H 9700 1550 60 0000 C CNN + 13 9700 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 69248DFA +P 9700 1700 +F 0 "U1" H 9750 1800 30 0000 C CNN +F 1 "PORT" H 9700 1700 30 0000 C CNN +F 2 "" H 9700 1700 60 0000 C CNN +F 3 "" H 9700 1700 60 0000 C CNN + 14 9700 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 69248EE3 +P 2700 1750 +F 0 "U1" H 2750 1850 30 0000 C CNN +F 1 "PORT" H 2700 1750 30 0000 C CNN +F 2 "" H 2700 1750 60 0000 C CNN +F 3 "" H 2700 1750 60 0000 C CNN + 1 2700 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 1500 1500 1500 +Wire Wire Line + 1300 1800 1500 1800 +Wire Wire Line + 1300 2050 1500 2050 +Wire Wire Line + 1200 2300 1500 2300 +NoConn ~ 1500 1500 +NoConn ~ 1500 1800 +NoConn ~ 1500 2050 +NoConn ~ 1500 2300 +Connection ~ 8350 3450 +Connection ~ 8750 6450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM161/LM161.sub b/library/SubcircuitLibrary/LM161/LM161.sub new file mode 100644 index 000000000..1665868ce --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161.sub @@ -0,0 +1,81 @@ +* Subcircuit LM161 +.subckt LM161 net-_q3-pad1_ ? net-_q1-pad2_ net-_q4-pad2_ ? net-_q11-pad3_ ? net-_d6-pad2_ net-_d7-pad2_ gnd net-_d4-pad2_ ? net-_d5-pad2_ net-_q28-pad1_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\lm161\lm161.cir +.include NPN.lib +.include D.lib +q3 net-_q3-pad1_ net-_d1-pad1_ net-_q3-pad3_ Q2N2222 +r4 net-_q3-pad1_ net-_d1-pad1_ 9k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148 +r3 net-_q3-pad3_ net-_q4-pad1_ 1450 +* u2 gnd net-_d3-pad2_ zener +q5 net-_q3-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q1-pad1_ 1450 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +r2 net-_q2-pad3_ net-_q11-pad3_ 400 +* u3 net-_q13-pad2_ net-_q5-pad3_ zener +q6 net-_q13-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_q3-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2222 +* u4 net-_q8-pad1_ net-_q7-pad3_ zener +q8 net-_q8-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ gnd Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ gnd Q2N2222 +q13 net-_q12-pad2_ net-_q13-pad2_ net-_q11-pad1_ Q2N2222 +r6 net-_q10-pad1_ net-_q10-pad2_ 1.3k +r8 net-_q12-pad1_ net-_q12-pad2_ 1.3k +r5 net-_q28-pad1_ net-_q10-pad1_ 1k +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r7 net-_q28-pad1_ net-_q12-pad1_ 1k +q9 net-_q10-pad2_ net-_q8-pad1_ net-_q11-pad1_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2222 +q15 net-_q14-pad1_ net-_q14-pad2_ net-_d5-pad2_ Q2N2222 +q17 net-_q14-pad1_ net-_q14-pad2_ net-_q17-pad3_ Q2N2222 +r9 net-_q28-pad1_ net-_q14-pad2_ 4k +r11 net-_q28-pad1_ net-_q17-pad3_ 1.4k +q19 net-_q17-pad3_ net-_q14-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q17-pad3_ net-_q14-pad1_ net-_d4-pad1_ Q2N2222 +r12 net-_q19-pad3_ net-_q24-pad2_ 235 +r13 net-_q24-pad2_ gnd 800 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q24 net-_d4-pad2_ net-_q24-pad2_ gnd Q2N2222 +q23 net-_q23-pad1_ net-_q17-pad3_ net-_d4-pad1_ Q2N2222 +r14 net-_q28-pad1_ net-_q23-pad1_ 100 +d6 gnd net-_d6-pad2_ 1N4148 +d5 gnd net-_d5-pad2_ 1N4148 +q16 net-_q16-pad1_ net-_q16-pad2_ net-_q12-pad1_ Q2N2222 +q18 net-_q16-pad1_ net-_q16-pad2_ net-_d6-pad2_ Q2N2222 +q20 net-_q16-pad1_ net-_q16-pad2_ net-_q20-pad3_ Q2N2222 +r10 net-_q28-pad1_ net-_q16-pad2_ 1k +r15 net-_q28-pad1_ net-_q20-pad3_ 1.4k +q22 net-_q20-pad3_ net-_q16-pad1_ net-_q22-pad3_ Q2N2222 +q25 net-_q20-pad3_ net-_q16-pad1_ net-_d7-pad1_ Q2N2222 +r17 net-_q27-pad2_ net-_q22-pad3_ 235 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +q27 net-_d7-pad2_ net-_q27-pad2_ gnd Q2N2222 +r16 net-_q27-pad2_ gnd 800 +q26 net-_q26-pad1_ net-_q20-pad3_ net-_d7-pad1_ Q2N2222 +r18 net-_q28-pad1_ net-_q26-pad1_ 100 +q28 net-_q28-pad1_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r21 net-_q28-pad1_ net-_q28-pad2_ 5k +r19 net-_q28-pad3_ net-_q2-pad2_ 3.2k +* u5 net-_q11-pad3_ net-_q28-pad2_ zener +r20 net-_q2-pad2_ net-_q11-pad2_ 387 +q29 net-_q11-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +a1 gnd net-_d3-pad2_ u2 +a2 net-_q13-pad2_ net-_q5-pad3_ u3 +a3 net-_q8-pad1_ net-_q7-pad3_ u4 +a4 net-_q11-pad3_ net-_q28-pad2_ u5 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM161 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM161/LM161_Previous_Values.xml b/library/SubcircuitLibrary/LM161/LM161_Previous_Values.xml new file mode 100644 index 000000000..0598d7de1 --- /dev/null +++ b/library/SubcircuitLibrary/LM161/LM161_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerzenerzenerC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM161/NPN.lib b/library/SubcircuitLibrary/LM161/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM161/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM161/analysis b/library/SubcircuitLibrary/LM161/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM161/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub-cache.lib b/library/SubcircuitLibrary/LM325_sub/LM325_sub-cache.lib new file mode 100644 index 000000000..c28cbe9d7 --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub-cache.lib @@ -0,0 +1,158 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir b/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir new file mode 100644 index 000000000..c3a19381b --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir @@ -0,0 +1,89 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\LM325_sub\LM325_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 10/22/25 19:11:53 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q7 Net-_Q13-Pad2_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_PNP +Q13 Net-_C2-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_PNP +Q20 Net-_Q16-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_PNP +Q18 Net-_Q10-Pad2_ Net-_Q18-Pad2_ Net-_C2-Pad1_ eSim_PNP +Q19 Net-_J1-Pad2_ Net-_C2-Pad1_ Net-_Q16-Pad1_ eSim_PNP +Q10 Net-_C2-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q14 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q14-Pad3_ eSim_NPN +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20p +R8 Net-_C1-Pad1_ Net-_C1-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +Q11 Net-_J1-Pad2_ Net-_C1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q15 Net-_J1-Pad2_ Net-_C2-Pad2_ Net-_Q14-Pad3_ eSim_PNP +Q5 Net-_Q13-Pad2_ Net-_C1-Pad2_ Net-_Q1-Pad1_ eSim_NPN +Q36 Net-_Q13-Pad3_ Net-_Q16-Pad1_ Net-_Q36-Pad3_ eSim_NPN +Q38 Net-_Q13-Pad3_ Net-_Q36-Pad3_ Net-_Q29-Pad2_ eSim_NPN +Q29 Net-_Q16-Pad1_ Net-_Q29-Pad2_ Net-_Q29-Pad3_ eSim_NPN +R27 Net-_Q29-Pad2_ Net-_Q29-Pad3_ 2.25 +R24 Net-_Q36-Pad3_ Net-_Q29-Pad3_ 10k +Q27 Net-_Q16-Pad1_ Net-_Q27-Pad2_ Net-_Q18-Pad2_ eSim_NPN +R28 Net-_Q29-Pad3_ Net-_R22-Pad2_ 300 +R22 Net-_Q27-Pad2_ Net-_R22-Pad2_ 1k +R29 Net-_Q18-Pad2_ Net-_C2-Pad2_ 15k +Q30 Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_C1-Pad2_ eSim_PNP +R30 Net-_C2-Pad2_ Net-_C3-Pad1_ 15k +R23 Net-_C1-Pad2_ Net-_Q28-Pad1_ 2k +Q31 Net-_C1-Pad2_ Net-_C1-Pad2_ Net-_C3-Pad1_ eSim_PNP +R16 Net-_C1-Pad2_ Net-_Q34-Pad2_ 15k +R17 Net-_Q34-Pad2_ Net-_C3-Pad1_ 15k +Q23 Net-_Q23-Pad1_ Net-_Q2-Pad1_ Net-_Q23-Pad3_ eSim_PNP +R13 Net-_C1-Pad2_ Net-_Q23-Pad3_ 390 +Q21 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_C1-Pad2_ eSim_PNP +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 30p +Q33 Net-_Q28-Pad1_ Net-_C3-Pad2_ Net-_Q33-Pad3_ eSim_NPN +Q37 Net-_Q28-Pad1_ Net-_Q33-Pad3_ Net-_C4-Pad2_ eSim_NPN +Q39 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q32-Pad2_ eSim_NPN +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 5p +R25 Net-_C4-Pad2_ Net-_Q32-Pad3_ 10k +R21 Net-_Q33-Pad3_ Net-_Q32-Pad3_ 20k +Q32 Net-_C3-Pad2_ Net-_Q32-Pad2_ Net-_Q32-Pad3_ eSim_NPN +R31 Net-_Q32-Pad2_ Net-_Q32-Pad3_ 2.25 +R20 Net-_Q23-Pad1_ Net-_Q34-Pad3_ 3.4k +Q34 Net-_Q28-Pad2_ Net-_Q34-Pad2_ Net-_Q34-Pad3_ eSim_PNP +R14 Net-_Q23-Pad1_ Net-_Q24-Pad3_ 3.4k +Q24 Net-_C3-Pad2_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_PNP +Q28 Net-_Q28-Pad1_ Net-_Q28-Pad2_ Net-_Q25-Pad2_ eSim_NPN +Q35 Net-_Q28-Pad2_ Net-_Q25-Pad2_ Net-_Q35-Pad3_ eSim_NPN +Q25 Net-_C3-Pad2_ Net-_Q25-Pad2_ Net-_Q25-Pad3_ eSim_NPN +R18 Net-_Q25-Pad2_ Net-_J1-Pad2_ 20k +R15 Net-_Q25-Pad3_ Net-_J1-Pad2_ 2k +R19 Net-_J1-Pad2_ Net-_Q35-Pad3_ 2k +R32 Net-_Q32-Pad3_ Net-_R26-Pad2_ 300 +R26 Net-_Q26-Pad2_ Net-_R26-Pad2_ 1k +Q22 Net-_C3-Pad2_ Net-_Q17-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q26 Net-_C3-Pad2_ Net-_Q26-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_J1-Pad2_ eSim_NPN +R11 Net-_Q16-Pad3_ Net-_Q17-Pad1_ 10k +Q16 Net-_Q16-Pad1_ Net-_J1-Pad3_ Net-_Q16-Pad3_ eSim_NPN +R12 Net-_Q12-Pad1_ Net-_Q24-Pad2_ 7.5k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +R10 Net-_C3-Pad1_ Net-_Q12-Pad3_ 23k +R9 Net-_J1-Pad2_ Net-_Q17-Pad2_ 3k +Q9 Net-_Q17-Pad2_ Net-_Q4-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R7 Net-_Q4-Pad2_ Net-_Q17-Pad2_ 3k +Q8 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_J1-Pad2_ eSim_NPN +R6 Net-_Q9-Pad3_ Net-_Q4-Pad1_ 1.5k +R5 Net-_Q6-Pad2_ Net-_Q12-Pad1_ 6.9k +R4 Net-_R4-Pad1_ Net-_Q6-Pad2_ 2k +U2 Net-_R4-Pad1_ Net-_C1-Pad2_ zener +Q6 Net-_C1-Pad2_ Net-_Q6-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R3 Net-_Q3-Pad3_ Net-_Q1-Pad3_ 3.9k +Q3 Net-_Q12-Pad1_ Net-_J1-Pad3_ Net-_Q3-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q4-Pad2_ Net-_J1-Pad2_ 515 +R1 Net-_Q1-Pad3_ Net-_Q4-Pad2_ 11k +U1 Net-_J1-Pad2_ Net-_J1-Pad3_ zener +J1 Net-_C1-Pad2_ Net-_J1-Pad2_ Net-_J1-Pad3_ eSim_NJF +U3 Net-_Q29-Pad3_ ? Net-_Q13-Pad3_ Net-_J1-Pad2_ Net-_R26-Pad2_ Net-_C3-Pad1_ Net-_C4-Pad1_ Net-_Q32-Pad3_ ? Net-_Q12-Pad1_ Net-_C1-Pad2_ ? Net-_R22-Pad2_ Net-_Q18-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir.out b/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir.out new file mode 100644 index 000000000..12425ea3d --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub.cir.out @@ -0,0 +1,99 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\lm325_sub\lm325_sub.cir + +.include PNP.lib +.include NJF.lib +.include NPN.lib +q7 net-_q13-pad2_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q13 net-_c2-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q20 net-_q16-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q18 net-_q10-pad2_ net-_q18-pad2_ net-_c2-pad1_ Q2N2907A +q19 net-_j1-pad2_ net-_c2-pad1_ net-_q16-pad1_ Q2N2907A +q10 net-_c2-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q14 net-_q10-pad2_ net-_q10-pad2_ net-_q14-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +r8 net-_c1-pad1_ net-_c1-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q10-pad3_ Q2N2907A +q15 net-_j1-pad2_ net-_c2-pad2_ net-_q14-pad3_ Q2N2907A +q5 net-_q13-pad2_ net-_c1-pad2_ net-_q1-pad1_ Q2N2222 +q36 net-_q13-pad3_ net-_q16-pad1_ net-_q36-pad3_ Q2N2222 +q38 net-_q13-pad3_ net-_q36-pad3_ net-_q29-pad2_ Q2N2222 +q29 net-_q16-pad1_ net-_q29-pad2_ net-_q29-pad3_ Q2N2222 +r27 net-_q29-pad2_ net-_q29-pad3_ 2.25 +r24 net-_q36-pad3_ net-_q29-pad3_ 10k +q27 net-_q16-pad1_ net-_q27-pad2_ net-_q18-pad2_ Q2N2222 +r28 net-_q29-pad3_ net-_r22-pad2_ 300 +r22 net-_q27-pad2_ net-_r22-pad2_ 1k +r29 net-_q18-pad2_ net-_c2-pad2_ 15k +q30 net-_q18-pad2_ net-_q18-pad2_ net-_c1-pad2_ Q2N2907A +r30 net-_c2-pad2_ net-_c3-pad1_ 15k +r23 net-_c1-pad2_ net-_q28-pad1_ 2k +q31 net-_c1-pad2_ net-_c1-pad2_ net-_c3-pad1_ Q2N2907A +r16 net-_c1-pad2_ net-_q34-pad2_ 15k +r17 net-_q34-pad2_ net-_c3-pad1_ 15k +q23 net-_q23-pad1_ net-_q2-pad1_ net-_q23-pad3_ Q2N2907A +r13 net-_c1-pad2_ net-_q23-pad3_ 390 +q21 net-_q2-pad1_ net-_q2-pad1_ net-_c1-pad2_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 30p +q33 net-_q28-pad1_ net-_c3-pad2_ net-_q33-pad3_ Q2N2222 +q37 net-_q28-pad1_ net-_q33-pad3_ net-_c4-pad2_ Q2N2222 +q39 net-_c4-pad1_ net-_c4-pad2_ net-_q32-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 5p +r25 net-_c4-pad2_ net-_q32-pad3_ 10k +r21 net-_q33-pad3_ net-_q32-pad3_ 20k +q32 net-_c3-pad2_ net-_q32-pad2_ net-_q32-pad3_ Q2N2222 +r31 net-_q32-pad2_ net-_q32-pad3_ 2.25 +r20 net-_q23-pad1_ net-_q34-pad3_ 3.4k +q34 net-_q28-pad2_ net-_q34-pad2_ net-_q34-pad3_ Q2N2907A +r14 net-_q23-pad1_ net-_q24-pad3_ 3.4k +q24 net-_c3-pad2_ net-_q24-pad2_ net-_q24-pad3_ Q2N2907A +q28 net-_q28-pad1_ net-_q28-pad2_ net-_q25-pad2_ Q2N2222 +q35 net-_q28-pad2_ net-_q25-pad2_ net-_q35-pad3_ Q2N2222 +q25 net-_c3-pad2_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +r18 net-_q25-pad2_ net-_j1-pad2_ 20k +r15 net-_q25-pad3_ net-_j1-pad2_ 2k +r19 net-_j1-pad2_ net-_q35-pad3_ 2k +r32 net-_q32-pad3_ net-_r26-pad2_ 300 +r26 net-_q26-pad2_ net-_r26-pad2_ 1k +q22 net-_c3-pad2_ net-_q17-pad2_ net-_j1-pad2_ Q2N2222 +q26 net-_c3-pad2_ net-_q26-pad2_ net-_j1-pad2_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad2_ Q2N2222 +r11 net-_q16-pad3_ net-_q17-pad1_ 10k +q16 net-_q16-pad1_ net-_j1-pad3_ net-_q16-pad3_ Q2N2222 +r12 net-_q12-pad1_ net-_q24-pad2_ 7.5k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222 +r10 net-_c3-pad1_ net-_q12-pad3_ 23k +r9 net-_j1-pad2_ net-_q17-pad2_ 3k +q9 net-_q17-pad2_ net-_q4-pad1_ net-_q9-pad3_ Q2N2907A +r7 net-_q4-pad2_ net-_q17-pad2_ 3k +q8 net-_q4-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222 +r6 net-_q9-pad3_ net-_q4-pad1_ 1.5k +r5 net-_q6-pad2_ net-_q12-pad1_ 6.9k +r4 net-_r4-pad1_ net-_q6-pad2_ 2k +* u2 net-_r4-pad1_ net-_c1-pad2_ zener +q6 net-_c1-pad2_ net-_q6-pad2_ net-_q12-pad1_ Q2N2222 +r3 net-_q3-pad3_ net-_q1-pad3_ 3.9k +q3 net-_q12-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +r2 net-_q4-pad2_ net-_j1-pad2_ 515 +r1 net-_q1-pad3_ net-_q4-pad2_ 11k +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +j1 net-_c1-pad2_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +* u3 net-_q29-pad3_ ? net-_q13-pad3_ net-_j1-pad2_ net-_r26-pad2_ net-_c3-pad1_ net-_c4-pad1_ net-_q32-pad3_ ? net-_q12-pad1_ net-_c1-pad2_ ? net-_r22-pad2_ net-_q18-pad2_ port +a1 net-_r4-pad1_ net-_c1-pad2_ u2 +a2 net-_j1-pad2_ net-_j1-pad3_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub.pro b/library/SubcircuitLibrary/LM325_sub/LM325_sub.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub.sch b/library/SubcircuitLibrary/LM325_sub/LM325_sub.sch new file mode 100644 index 000000000..ba2ccb22b --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub.sch @@ -0,0 +1,1559 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx 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60 0000 C CNN + 4 10050 11950 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub.sub b/library/SubcircuitLibrary/LM325_sub/LM325_sub.sub new file mode 100644 index 000000000..1bf35b622 --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub.sub @@ -0,0 +1,93 @@ +* Subcircuit LM325_sub +.subckt LM325_sub net-_q29-pad3_ ? net-_q13-pad3_ net-_j1-pad2_ net-_r26-pad2_ net-_c3-pad1_ net-_c4-pad1_ net-_q32-pad3_ ? net-_q12-pad1_ net-_c1-pad2_ ? net-_r22-pad2_ net-_q18-pad2_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\lm325_sub\lm325_sub.cir +.include PNP.lib +.include NJF.lib +.include NPN.lib +q7 net-_q13-pad2_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q13 net-_c2-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q20 net-_q16-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2907A +q18 net-_q10-pad2_ net-_q18-pad2_ net-_c2-pad1_ Q2N2907A +q19 net-_j1-pad2_ net-_c2-pad1_ net-_q16-pad1_ Q2N2907A +q10 net-_c2-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q14 net-_q10-pad2_ net-_q10-pad2_ net-_q14-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +r8 net-_c1-pad1_ net-_c1-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q10-pad3_ Q2N2907A +q15 net-_j1-pad2_ net-_c2-pad2_ net-_q14-pad3_ Q2N2907A +q5 net-_q13-pad2_ net-_c1-pad2_ net-_q1-pad1_ Q2N2222 +q36 net-_q13-pad3_ net-_q16-pad1_ net-_q36-pad3_ Q2N2222 +q38 net-_q13-pad3_ net-_q36-pad3_ net-_q29-pad2_ Q2N2222 +q29 net-_q16-pad1_ net-_q29-pad2_ net-_q29-pad3_ Q2N2222 +r27 net-_q29-pad2_ net-_q29-pad3_ 2.25 +r24 net-_q36-pad3_ net-_q29-pad3_ 10k +q27 net-_q16-pad1_ net-_q27-pad2_ net-_q18-pad2_ Q2N2222 +r28 net-_q29-pad3_ net-_r22-pad2_ 300 +r22 net-_q27-pad2_ net-_r22-pad2_ 1k +r29 net-_q18-pad2_ net-_c2-pad2_ 15k +q30 net-_q18-pad2_ net-_q18-pad2_ net-_c1-pad2_ Q2N2907A +r30 net-_c2-pad2_ net-_c3-pad1_ 15k +r23 net-_c1-pad2_ net-_q28-pad1_ 2k +q31 net-_c1-pad2_ net-_c1-pad2_ net-_c3-pad1_ Q2N2907A +r16 net-_c1-pad2_ net-_q34-pad2_ 15k +r17 net-_q34-pad2_ net-_c3-pad1_ 15k +q23 net-_q23-pad1_ net-_q2-pad1_ net-_q23-pad3_ Q2N2907A +r13 net-_c1-pad2_ net-_q23-pad3_ 390 +q21 net-_q2-pad1_ net-_q2-pad1_ net-_c1-pad2_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 30p +q33 net-_q28-pad1_ net-_c3-pad2_ net-_q33-pad3_ Q2N2222 +q37 net-_q28-pad1_ net-_q33-pad3_ net-_c4-pad2_ Q2N2222 +q39 net-_c4-pad1_ net-_c4-pad2_ net-_q32-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 5p +r25 net-_c4-pad2_ net-_q32-pad3_ 10k +r21 net-_q33-pad3_ net-_q32-pad3_ 20k +q32 net-_c3-pad2_ net-_q32-pad2_ net-_q32-pad3_ Q2N2222 +r31 net-_q32-pad2_ net-_q32-pad3_ 2.25 +r20 net-_q23-pad1_ net-_q34-pad3_ 3.4k +q34 net-_q28-pad2_ net-_q34-pad2_ net-_q34-pad3_ Q2N2907A +r14 net-_q23-pad1_ net-_q24-pad3_ 3.4k +q24 net-_c3-pad2_ net-_q24-pad2_ net-_q24-pad3_ Q2N2907A +q28 net-_q28-pad1_ net-_q28-pad2_ net-_q25-pad2_ Q2N2222 +q35 net-_q28-pad2_ net-_q25-pad2_ net-_q35-pad3_ Q2N2222 +q25 net-_c3-pad2_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +r18 net-_q25-pad2_ net-_j1-pad2_ 20k +r15 net-_q25-pad3_ net-_j1-pad2_ 2k +r19 net-_j1-pad2_ net-_q35-pad3_ 2k +r32 net-_q32-pad3_ net-_r26-pad2_ 300 +r26 net-_q26-pad2_ net-_r26-pad2_ 1k +q22 net-_c3-pad2_ net-_q17-pad2_ net-_j1-pad2_ Q2N2222 +q26 net-_c3-pad2_ net-_q26-pad2_ net-_j1-pad2_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad2_ Q2N2222 +r11 net-_q16-pad3_ net-_q17-pad1_ 10k +q16 net-_q16-pad1_ net-_j1-pad3_ net-_q16-pad3_ Q2N2222 +r12 net-_q12-pad1_ net-_q24-pad2_ 7.5k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222 +r10 net-_c3-pad1_ net-_q12-pad3_ 23k +r9 net-_j1-pad2_ net-_q17-pad2_ 3k +q9 net-_q17-pad2_ net-_q4-pad1_ net-_q9-pad3_ Q2N2907A +r7 net-_q4-pad2_ net-_q17-pad2_ 3k +q8 net-_q4-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222 +r6 net-_q9-pad3_ net-_q4-pad1_ 1.5k +r5 net-_q6-pad2_ net-_q12-pad1_ 6.9k +r4 net-_r4-pad1_ net-_q6-pad2_ 2k +* u2 net-_r4-pad1_ net-_c1-pad2_ zener +q6 net-_c1-pad2_ net-_q6-pad2_ net-_q12-pad1_ Q2N2222 +r3 net-_q3-pad3_ net-_q1-pad3_ 3.9k +q3 net-_q12-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +r2 net-_q4-pad2_ net-_j1-pad2_ 515 +r1 net-_q1-pad3_ net-_q4-pad2_ 11k +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +j1 net-_c1-pad2_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +a1 net-_r4-pad1_ net-_c1-pad2_ u2 +a2 net-_j1-pad2_ net-_j1-pad3_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM325_sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM325_sub/LM325_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM325_sub/LM325_sub_Previous_Values.xml new file mode 100644 index 000000000..05318af43 --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/LM325_sub_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\JFET\NJF.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM325_sub/NJF.lib b/library/SubcircuitLibrary/LM325_sub/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM325_sub/NPN.lib b/library/SubcircuitLibrary/LM325_sub/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM325_sub/PNP.lib b/library/SubcircuitLibrary/LM325_sub/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM325_sub/analysis b/library/SubcircuitLibrary/LM325_sub/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM325_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC100EL1648/D.lib b/library/SubcircuitLibrary/MC100EL1648/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648-cache.lib b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648-cache.lib new file mode 100644 index 000000000..7e9c6731b --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir new file mode 100644 index 000000000..626b36e33 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir @@ -0,0 +1,37 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\MC100EL1648\MC100EL1648.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 11/29/25 21:04:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad2_ Net-_Q1-Pad2_ Net-_D1-Pad1_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R3 Net-_Q1-Pad3_ Net-_Q5-Pad3_ 400 +R2 Net-_Q3-Pad2_ Net-_Q1-Pad1_ 1.6k +R1 Net-_Q3-Pad1_ Net-_Q3-Pad2_ 800 +R4 Net-_Q3-Pad1_ Net-_Q1-Pad2_ 1.36k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad1_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q1-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad1_ Net-_Q4-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R5 Net-_Q4-Pad3_ Net-_Q5-Pad1_ 330 +Q5 Net-_Q5-Pad1_ Net-_D2-Pad2_ Net-_Q5-Pad3_ eSim_NPN +R6 Net-_D2-Pad2_ Net-_R6-Pad2_ 16k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R7 Net-_Q3-Pad1_ Net-_D2-Pad1_ 3.1k +Q7 Net-_D2-Pad1_ Net-_Q7-Pad2_ Net-_Q7-Pad3_ eSim_NPN +R8 Net-_Q7-Pad3_ Net-_Q5-Pad3_ 82 +Q8 Net-_Q8-Pad1_ Net-_Q4-Pad1_ Net-_Q7-Pad2_ eSim_NPN +R10 Net-_Q7-Pad2_ Net-_Q5-Pad3_ 400 +R9 Net-_Q3-Pad1_ Net-_Q8-Pad1_ 660 +Q9 Net-_Q3-Pad1_ Net-_Q8-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R12 Net-_Q3-Pad1_ Net-_Q10-Pad1_ 167 +R11 Net-_Q10-Pad3_ Net-_Q5-Pad3_ 660 +Q11 Net-_Q11-Pad1_ Net-_Q10-Pad1_ Net-_Q11-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q5-Pad3_ 510 +U1 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ Net-_D2-Pad1_ Net-_R6-Pad2_ Net-_D1-Pad2_ Net-_Q1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir.out b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir.out new file mode 100644 index 000000000..701f50045 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.cir.out @@ -0,0 +1,40 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\mc100el1648\mc100el1648.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad2_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r3 net-_q1-pad3_ net-_q5-pad3_ 400 +r2 net-_q3-pad2_ net-_q1-pad1_ 1.6k +r1 net-_q3-pad1_ net-_q3-pad2_ 800 +r4 net-_q3-pad1_ net-_q1-pad2_ 1.36k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q1-pad2_ net-_q4-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q4-pad1_ net-_q4-pad3_ Q2N2222 +r5 net-_q4-pad3_ net-_q5-pad1_ 330 +q5 net-_q5-pad1_ net-_d2-pad2_ net-_q5-pad3_ Q2N2222 +r6 net-_d2-pad2_ net-_r6-pad2_ 16k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r7 net-_q3-pad1_ net-_d2-pad1_ 3.1k +q7 net-_d2-pad1_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 +r8 net-_q7-pad3_ net-_q5-pad3_ 82 +q8 net-_q8-pad1_ net-_q4-pad1_ net-_q7-pad2_ Q2N2222 +r10 net-_q7-pad2_ net-_q5-pad3_ 400 +r9 net-_q3-pad1_ net-_q8-pad1_ 660 +q9 net-_q3-pad1_ net-_q8-pad1_ net-_q10-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad1_ net-_q10-pad3_ Q2N2222 +r12 net-_q3-pad1_ net-_q10-pad1_ 167 +r11 net-_q10-pad3_ net-_q5-pad3_ 660 +q11 net-_q11-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q5-pad3_ 510 +* u1 net-_q4-pad1_ net-_q3-pad1_ net-_q11-pad1_ net-_q11-pad3_ net-_d2-pad1_ net-_r6-pad2_ net-_d1-pad2_ net-_q1-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.pro b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sch b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sch new file mode 100644 index 000000000..516b15ee4 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sch @@ -0,0 +1,588 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC100EL1648-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 692B114E +P 3200 4150 +F 0 "Q1" H 3100 4200 50 0000 R CNN +F 1 "eSim_NPN" H 3150 4300 50 0000 R CNN +F 2 "" H 3400 4250 29 0000 C CNN +F 3 "" H 3200 4150 60 0000 C CNN + 1 3200 4150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 692B114F +P 3900 4150 +F 0 "Q2" H 3800 4200 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4300 50 0000 R CNN +F 2 "" H 4100 4250 29 0000 C CNN +F 3 "" H 3900 4150 60 0000 C CNN + 1 3900 4150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 692B1150 +P 3800 4700 +F 0 "D1" H 3800 4800 50 0000 C CNN +F 1 "eSim_Diode" H 3800 4600 50 0000 C CNN +F 2 "" H 3800 4700 60 0000 C CNN +F 3 "" H 3800 4700 60 0000 C CNN + 1 3800 4700 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 692B1151 +P 3050 4700 +F 0 "R3" H 3100 4830 50 0000 C CNN +F 1 "400" H 3100 4650 50 0000 C CNN +F 2 "" H 3100 4680 30 0000 C CNN +F 3 "" V 3100 4750 30 0000 C CNN + 1 3050 4700 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 692B1152 +P 3050 3400 +F 0 "R2" H 3100 3530 50 0000 C CNN +F 1 "1.6k" H 3100 3350 50 0000 C CNN +F 2 "" H 3100 3380 30 0000 C CNN +F 3 "" V 3100 3450 30 0000 C CNN + 1 3050 3400 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R1 +U 1 1 692B1153 +P 3050 2900 +F 0 "R1" H 3100 3030 50 0000 C CNN +F 1 "800" H 3100 2850 50 0000 C CNN +F 2 "" H 3100 2880 30 0000 C CNN +F 3 "" V 3100 2950 30 0000 C CNN + 1 3050 2900 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R4 +U 1 1 692B1154 +P 3750 2900 +F 0 "R4" H 3800 3030 50 0000 C CNN +F 1 "1.36k" H 3800 2850 50 0000 C CNN +F 2 "" H 3800 2880 30 0000 C CNN +F 3 "" V 3800 2950 30 0000 C CNN + 1 3750 2900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 692B1155 +P 4550 3150 +F 0 "Q3" H 4450 3200 50 0000 R CNN +F 1 "eSim_NPN" H 4500 3300 50 0000 R CNN +F 2 "" H 4750 3250 29 0000 C CNN +F 3 "" H 4550 3150 60 0000 C CNN + 1 4550 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 692B1156 +P 5400 4150 +F 0 "Q4" H 5300 4200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4300 50 0000 R CNN +F 2 "" H 5600 4250 29 0000 C CNN +F 3 "" H 5400 4150 60 0000 C CNN + 1 5400 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 692B1157 +P 6050 4150 +F 0 "Q6" H 5950 4200 50 0000 R CNN +F 1 "eSim_NPN" H 6000 4300 50 0000 R CNN +F 2 "" H 6250 4250 29 0000 C CNN +F 3 "" H 6050 4150 60 0000 C CNN + 1 6050 4150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 692B1158 +P 5650 4600 +F 0 "R5" H 5700 4730 50 0000 C CNN +F 1 "330" H 5700 4550 50 0000 C CNN +F 2 "" H 5700 4580 30 0000 C CNN +F 3 "" V 5700 4650 30 0000 C CNN + 1 5650 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 692B1159 +P 5800 5050 +F 0 "Q5" H 5700 5100 50 0000 R CNN +F 1 "eSim_NPN" H 5750 5200 50 0000 R CNN +F 2 "" H 6000 5150 29 0000 C CNN +F 3 "" H 5800 5050 60 0000 C CNN + 1 5800 5050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R6 +U 1 1 692B115A +P 6100 5200 +F 0 "R6" H 6150 5330 50 0000 C CNN +F 1 "16k" H 6150 5150 50 0000 C CNN +F 2 "" H 6150 5180 30 0000 C CNN +F 3 "" V 6150 5250 30 0000 C CNN + 1 6100 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 692B115B +P 6350 4850 +F 0 "D2" H 6350 4950 50 0000 C CNN +F 1 "eSim_Diode" H 6350 4750 50 0000 C CNN +F 2 "" H 6350 4850 60 0000 C CNN +F 3 "" H 6350 4850 60 0000 C CNN + 1 6350 4850 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 692B115C +P 6550 2900 +F 0 "R7" H 6600 3030 50 0000 C CNN +F 1 "3.1k" H 6600 2850 50 0000 C CNN +F 2 "" H 6600 2880 30 0000 C CNN +F 3 "" V 6600 2950 30 0000 C CNN + 1 6550 2900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 692B115D +P 7100 4650 +F 0 "Q7" H 7000 4700 50 0000 R CNN +F 1 "eSim_NPN" H 7050 4800 50 0000 R CNN +F 2 "" H 7300 4750 29 0000 C CNN +F 3 "" H 7100 4650 60 0000 C CNN + 1 7100 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3100 4350 3100 4600 +Wire Wire Line + 4100 4150 5200 4150 +Wire Wire Line + 4200 3850 4200 4450 +Wire Wire Line + 4200 3850 3800 3850 +Wire Wire Line + 3800 3100 3800 3950 +Wire Wire Line + 3400 4150 3550 4150 +Wire Wire Line + 3550 4150 3550 4450 +Wire Wire Line + 3550 4450 4200 4450 +Connection ~ 4200 4150 +Wire Wire Line + 3800 4350 3800 4550 +Wire Wire Line + 3100 3600 3100 3950 +Wire Wire Line + 3100 3100 3100 3300 +Connection ~ 3800 3850 +Wire Wire Line + 3100 2800 3100 2700 +Wire Wire Line + 3100 2700 8250 2700 +Wire Wire Line + 3800 2700 3800 2800 +Wire Wire Line + 4350 3150 3100 3150 +Connection ~ 3100 3150 +Wire Wire Line + 4650 2700 4650 2950 +Connection ~ 3800 2700 +Wire Wire Line + 3100 3650 8550 3650 +Wire Wire Line + 4650 3650 4650 3350 +Connection ~ 3100 3650 +Wire Wire Line + 3800 4850 3800 5400 +Wire Wire Line + 4800 4150 4800 5400 +Connection ~ 4800 4150 +Wire Wire Line + 5500 3950 5500 3850 +Wire Wire Line + 5050 3850 7200 3850 +Wire Wire Line + 5050 3850 5050 5400 +Connection ~ 5500 3850 +Wire Wire Line + 6250 4150 6300 4150 +Wire Wire Line + 6300 4150 6300 3850 +Wire Wire Line + 5950 3950 5950 2350 +Connection ~ 5950 2700 +Connection ~ 4650 2700 +Wire Wire Line + 5500 4350 5500 4400 +Wire Wire Line + 5500 4400 5950 4400 +Wire Wire Line + 5950 4400 5950 4350 +Wire Wire Line + 5700 4500 5700 4400 +Connection ~ 5700 4400 +Wire Wire Line + 5700 4850 5700 4800 +Wire Wire Line + 3100 4900 3100 5300 +Wire Wire Line + 3100 5300 8900 5300 +Wire Wire Line + 5700 5300 5700 5250 +Wire Wire Line + 6000 5050 6150 5050 +Wire Wire Line + 6150 4850 6150 5100 +Wire Wire Line + 6150 5400 6150 5500 +Wire Wire Line + 6150 4850 6200 4850 +Connection ~ 6150 5050 +Wire Wire Line + 6500 4850 6750 4850 +Wire Wire Line + 6600 3100 6600 5500 +Wire Wire Line + 6600 2700 6600 2800 +Connection ~ 6600 4850 +Wire Wire Line + 6750 4850 6750 4450 +Wire Wire Line + 6750 4450 7000 4450 +$Comp +L eSim_R R8 +U 1 1 692B115E +P 6950 5050 +F 0 "R8" H 7000 5180 50 0000 C CNN +F 1 "82" H 7000 5000 50 0000 C CNN +F 2 "" H 7000 5030 30 0000 C CNN +F 3 "" V 7000 5100 30 0000 C CNN + 1 6950 5050 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 4950 7000 4850 +Wire Wire Line + 7000 5300 7000 5250 +Connection ~ 5700 5300 +$Comp +L eSim_NPN Q8 +U 1 1 692B115F +P 7400 3850 +F 0 "Q8" H 7300 3900 50 0000 R CNN +F 1 "eSim_NPN" H 7350 4000 50 0000 R CNN +F 2 "" H 7600 3950 29 0000 C CNN +F 3 "" H 7400 3850 60 0000 C CNN + 1 7400 3850 + 1 0 0 -1 +$EndComp +Connection ~ 6300 3850 +Wire Wire Line + 7500 4050 7500 4750 +Wire Wire Line + 7500 4650 7300 4650 +$Comp +L eSim_R R10 +U 1 1 692B1160 +P 7450 4850 +F 0 "R10" H 7500 4980 50 0000 C CNN +F 1 "400" H 7500 4800 50 0000 C CNN +F 2 "" H 7500 4830 30 0000 C CNN +F 3 "" V 7500 4900 30 0000 C CNN + 1 7450 4850 + 0 1 1 0 +$EndComp +Connection ~ 7500 4650 +Wire Wire Line + 7500 5300 7500 5050 +Connection ~ 7000 5300 +$Comp +L eSim_R R9 +U 1 1 692B1161 +P 7450 2900 +F 0 "R9" H 7500 3030 50 0000 C CNN +F 1 "660" H 7500 2850 50 0000 C CNN +F 2 "" H 7500 2880 30 0000 C CNN +F 3 "" V 7500 2950 30 0000 C CNN + 1 7450 2900 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 2700 7500 2800 +Connection ~ 6600 2700 +Wire Wire Line + 7500 3100 7500 3650 +$Comp +L eSim_NPN Q9 +U 1 1 692B1162 +P 7850 3300 +F 0 "Q9" H 7750 3350 50 0000 R CNN +F 1 "eSim_NPN" H 7800 3450 50 0000 R CNN +F 2 "" H 8050 3400 29 0000 C CNN +F 3 "" H 7850 3300 60 0000 C CNN + 1 7850 3300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 692B1163 +P 8350 3300 +F 0 "Q10" H 8250 3350 50 0000 R CNN +F 1 "eSim_NPN" H 8300 3450 50 0000 R CNN +F 2 "" H 8550 3400 29 0000 C CNN +F 3 "" H 8350 3300 60 0000 C CNN + 1 8350 3300 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7950 2700 7950 3100 +Connection ~ 7500 2700 +Wire Wire Line + 7650 3300 7500 3300 +Connection ~ 7500 3300 +Wire Wire Line + 7950 3500 7950 3600 +Wire Wire Line + 7950 3600 8250 3600 +Wire Wire Line + 8250 3600 8250 3500 +$Comp +L eSim_R R12 +U 1 1 692B1164 +P 8200 2850 +F 0 "R12" H 8250 2980 50 0000 C CNN +F 1 "167" H 8250 2800 50 0000 C CNN +F 2 "" H 8250 2830 30 0000 C CNN +F 3 "" V 8250 2900 30 0000 C CNN + 1 8200 2850 + 0 1 1 0 +$EndComp +Wire Wire Line + 8250 3100 8250 3050 +Wire Wire Line + 8250 2700 8250 2750 +Connection ~ 7950 2700 +$Comp +L eSim_R R11 +U 1 1 692B1165 +P 8050 4900 +F 0 "R11" H 8100 5030 50 0000 C CNN +F 1 "660" H 8100 4850 50 0000 C CNN +F 2 "" H 8100 4880 30 0000 C CNN +F 3 "" V 8100 4950 30 0000 C CNN + 1 8050 4900 + 0 1 1 0 +$EndComp +Wire Wire Line + 8100 4800 8100 3600 +Connection ~ 8100 3600 +Wire Wire Line + 8100 5300 8100 5100 +Connection ~ 7500 5300 +Wire Wire Line + 8550 3650 8550 3300 +Connection ~ 4650 3650 +Wire Wire Line + 8250 3100 8600 3100 +$Comp +L eSim_NPN Q11 +U 1 1 692B1166 +P 8800 3100 +F 0 "Q11" H 8700 3150 50 0000 R CNN +F 1 "eSim_NPN" H 8750 3250 50 0000 R CNN +F 2 "" H 9000 3200 29 0000 C CNN +F 3 "" H 8800 3100 60 0000 C CNN + 1 8800 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8900 2900 8900 2200 +$Comp +L eSim_R R13 +U 1 1 692B1167 +P 8850 4400 +F 0 "R13" H 8900 4530 50 0000 C CNN +F 1 "510" H 8900 4350 50 0000 C CNN +F 2 "" H 8900 4380 30 0000 C CNN +F 3 "" V 8900 4450 30 0000 C CNN + 1 8850 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8900 3300 8900 4300 +Wire Wire Line + 8900 5300 8900 4600 +Connection ~ 8100 5300 +Wire Wire Line + 8900 3700 9100 3700 +Connection ~ 8900 3700 +Connection ~ 8250 3100 +Connection ~ 6450 4100 +$Comp +L PORT U1 +U 1 1 692B12C1 +P 5050 5650 +F 0 "U1" H 5100 5750 30 0000 C CNN +F 1 "PORT" H 5050 5650 30 0000 C CNN +F 2 "" H 5050 5650 60 0000 C CNN +F 3 "" H 5050 5650 60 0000 C CNN + 1 5050 5650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 692B137A +P 5950 2100 +F 0 "U1" H 6000 2200 30 0000 C CNN +F 1 "PORT" H 5950 2100 30 0000 C CNN +F 2 "" H 5950 2100 60 0000 C CNN +F 3 "" H 5950 2100 60 0000 C CNN + 2 5950 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 692B1427 +P 8650 2200 +F 0 "U1" H 8700 2300 30 0000 C CNN +F 1 "PORT" H 8650 2200 30 0000 C CNN +F 2 "" H 8650 2200 60 0000 C CNN +F 3 "" H 8650 2200 60 0000 C CNN + 3 8650 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 692B14D6 +P 9350 3700 +F 0 "U1" H 9400 3800 30 0000 C CNN +F 1 "PORT" H 9350 3700 30 0000 C CNN +F 2 "" H 9350 3700 60 0000 C CNN +F 3 "" H 9350 3700 60 0000 C CNN + 4 9350 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 692B158D +P 6600 5750 +F 0 "U1" H 6650 5850 30 0000 C CNN +F 1 "PORT" H 6600 5750 30 0000 C CNN +F 2 "" H 6600 5750 60 0000 C CNN +F 3 "" H 6600 5750 60 0000 C CNN + 5 6600 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 692B1636 +P 6150 5750 +F 0 "U1" H 6200 5850 30 0000 C CNN +F 1 "PORT" H 6150 5750 30 0000 C CNN +F 2 "" H 6150 5750 60 0000 C CNN +F 3 "" H 6150 5750 60 0000 C CNN + 6 6150 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 692B16D5 +P 3800 5650 +F 0 "U1" H 3850 5750 30 0000 C CNN +F 1 "PORT" H 3800 5650 30 0000 C CNN +F 2 "" H 3800 5650 60 0000 C CNN +F 3 "" H 3800 5650 60 0000 C CNN + 7 3800 5650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 692B1768 +P 4800 5650 +F 0 "U1" H 4850 5750 30 0000 C CNN +F 1 "PORT" H 4800 5650 30 0000 C CNN +F 2 "" H 4800 5650 60 0000 C CNN +F 3 "" H 4800 5650 60 0000 C CNN + 8 4800 5650 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sub b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sub new file mode 100644 index 000000000..02f9767c2 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648.sub @@ -0,0 +1,34 @@ +* Subcircuit MC100EL1648 +.subckt MC100EL1648 net-_q4-pad1_ net-_q3-pad1_ net-_q11-pad1_ net-_q11-pad3_ net-_d2-pad1_ net-_r6-pad2_ net-_d1-pad2_ net-_q1-pad2_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\mc100el1648\mc100el1648.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad2_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r3 net-_q1-pad3_ net-_q5-pad3_ 400 +r2 net-_q3-pad2_ net-_q1-pad1_ 1.6k +r1 net-_q3-pad1_ net-_q3-pad2_ 800 +r4 net-_q3-pad1_ net-_q1-pad2_ 1.36k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q1-pad2_ net-_q4-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q4-pad1_ net-_q4-pad3_ Q2N2222 +r5 net-_q4-pad3_ net-_q5-pad1_ 330 +q5 net-_q5-pad1_ net-_d2-pad2_ net-_q5-pad3_ Q2N2222 +r6 net-_d2-pad2_ net-_r6-pad2_ 16k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r7 net-_q3-pad1_ net-_d2-pad1_ 3.1k +q7 net-_d2-pad1_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 +r8 net-_q7-pad3_ net-_q5-pad3_ 82 +q8 net-_q8-pad1_ net-_q4-pad1_ net-_q7-pad2_ Q2N2222 +r10 net-_q7-pad2_ net-_q5-pad3_ 400 +r9 net-_q3-pad1_ net-_q8-pad1_ 660 +q9 net-_q3-pad1_ net-_q8-pad1_ net-_q10-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad1_ net-_q10-pad3_ Q2N2222 +r12 net-_q3-pad1_ net-_q10-pad1_ 167 +r11 net-_q10-pad3_ net-_q5-pad3_ 660 +q11 net-_q11-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q5-pad3_ 510 +* Control Statements + +.ends MC100EL1648 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC100EL1648/MC100EL1648_Previous_Values.xml b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648_Previous_Values.xml new file mode 100644 index 000000000..3c076c01f --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/MC100EL1648_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC100EL1648/NPN.lib b/library/SubcircuitLibrary/MC100EL1648/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC100EL1648/analysis b/library/SubcircuitLibrary/MC100EL1648/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MC100EL1648/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS194/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS194/3_and.cir b/library/SubcircuitLibrary/SN74LS194/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS194/3_and.cir.out b/library/SubcircuitLibrary/SN74LS194/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS194/3_and.pro b/library/SubcircuitLibrary/SN74LS194/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS194/3_and.sch b/library/SubcircuitLibrary/SN74LS194/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS194/3_and.sub b/library/SubcircuitLibrary/SN74LS194/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS194/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor-cache.lib b/library/SubcircuitLibrary/SN74LS194/3_nor-cache.lib new file mode 100644 index 000000000..a0171f291 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor.cir b/library/SubcircuitLibrary/SN74LS194/3_nor.cir new file mode 100644 index 000000000..7d3f12736 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor.cir @@ -0,0 +1,14 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\3_nor\3_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 12/13/25 16:14:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_or +U4 Net-_U3-Pad3_ Net-_U1-Pad4_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor.cir.out b/library/SubcircuitLibrary/SN74LS194/3_nor.cir.out new file mode 100644 index 000000000..8662cc3af --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor.cir.out @@ -0,0 +1,24 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\3_nor\3_nor.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u3-pad3_ d_or +* u4 net-_u3-pad3_ net-_u1-pad4_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 net-_u3-pad3_ net-_u1-pad4_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor.pro b/library/SubcircuitLibrary/SN74LS194/3_nor.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor.sch b/library/SubcircuitLibrary/SN74LS194/3_nor.sch new file mode 100644 index 000000000..7e9b6f9f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor.sch @@ -0,0 +1,153 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 693D4349 +P 4900 2850 +F 0 "U2" H 4900 2850 60 0000 C CNN +F 1 "d_or" H 4900 2950 60 0000 C CNN +F 2 "" H 4900 2850 60 0000 C CNN +F 3 "" H 4900 2850 60 0000 C CNN + 1 4900 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 693D43A8 +P 5250 3200 +F 0 "U3" H 5250 3200 60 0000 C CNN +F 1 "d_or" H 5250 3300 60 0000 C CNN +F 2 "" H 5250 3200 60 0000 C CNN +F 3 "" H 5250 3200 60 0000 C CNN + 1 5250 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 693D4429 +P 6200 3150 +F 0 "U4" H 6200 3050 60 0000 C CNN +F 1 "d_inverter" H 6200 3300 60 0000 C CNN +F 2 "" H 6250 3100 60 0000 C CNN +F 3 "" H 6250 3100 60 0000 C CNN + 1 6200 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 2750 4250 2750 +Wire Wire Line + 4450 2850 4250 2850 +Wire Wire Line + 5350 2800 5400 2800 +Wire Wire Line + 5400 2800 5400 3000 +Wire Wire Line + 5400 3000 4550 3000 +Wire Wire Line + 4550 3000 4550 3100 +Wire Wire Line + 4550 3100 4800 3100 +Wire Wire Line + 4800 3200 4350 3200 +Wire Wire Line + 5700 3150 5900 3150 +Wire Wire Line + 6500 3150 6650 3150 +$Comp +L PORT U1 +U 4 1 693D44E1 +P 6650 3400 +F 0 "U1" H 6700 3500 30 0000 C CNN +F 1 "PORT" H 6650 3400 30 0000 C CNN +F 2 "" H 6650 3400 60 0000 C CNN +F 3 "" H 6650 3400 60 0000 C CNN + 4 6650 3400 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 693D4566 +P 4100 3200 +F 0 "U1" H 4150 3300 30 0000 C CNN +F 1 "PORT" H 4100 3200 30 0000 C CNN +F 2 "" H 4100 3200 60 0000 C CNN +F 3 "" H 4100 3200 60 0000 C CNN + 3 4100 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 693D45B1 +P 4000 2750 +F 0 "U1" H 4050 2850 30 0000 C CNN +F 1 "PORT" H 4000 2750 30 0000 C CNN +F 2 "" H 4000 2750 60 0000 C CNN +F 3 "" H 4000 2750 60 0000 C CNN + 1 4000 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 693D45E6 +P 4000 2850 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4000 2850 30 0000 C CNN +F 2 "" H 4000 2850 60 0000 C CNN +F 3 "" H 4000 2850 60 0000 C CNN + 2 4000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor.sub b/library/SubcircuitLibrary/SN74LS194/3_nor.sub new file mode 100644 index 000000000..bd3bcb32e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor.sub @@ -0,0 +1,18 @@ +* Subcircuit 3_nor +.subckt 3_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\3_nor\3_nor.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u3-pad3_ d_or +* u4 net-_u3-pad3_ net-_u1-pad4_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 net-_u3-pad3_ net-_u1-pad4_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 3_nor \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS194/3_nor_Previous_Values.xml new file mode 100644 index 000000000..0a0060e94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/3_nor_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194-cache.lib b/library/SubcircuitLibrary/SN74LS194/SN74LS194-cache.lib new file mode 100644 index 000000000..41a3255b9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir b/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir new file mode 100644 index 000000000..794bfea32 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir @@ -0,0 +1,48 @@ +* C:\Users\AJAY\OneDrive\Desktop\FOSSEE2.3\eSim\library\SubcircuitLibrary\SN74LS194\SN74LS194.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/17/26 19:34:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U15-Pad1_ Net-_U1-Pad2_ Net-_U6-Pad3_ d_and +U11 Net-_U1-Pad3_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad14_ Net-_U13-Pad2_ Net-_U12-Pad1_ d_and +U14 Net-_U14-Pad1_ Net-_U10-Pad3_ ? Net-_U1-Pad1_ Net-_U1-Pad15_ ? d_dff +U9 Net-_U8-Pad2_ Net-_U14-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U1-Pad15_ Net-_U15-Pad3_ d_and +U19 Net-_U1-Pad4_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_and +U21 Net-_U1-Pad13_ Net-_U13-Pad2_ Net-_U20-Pad1_ d_and +U22 Net-_U18-Pad2_ Net-_U10-Pad3_ ? Net-_U1-Pad1_ Net-_U1-Pad14_ ? d_dff +U18 Net-_U17-Pad2_ Net-_U18-Pad2_ d_inverter +U23 Net-_U15-Pad1_ Net-_U1-Pad14_ Net-_U23-Pad3_ d_and +U27 Net-_U1-Pad5_ Net-_U11-Pad2_ Net-_U27-Pad3_ d_and +U29 Net-_U1-Pad12_ Net-_U13-Pad2_ Net-_U28-Pad1_ d_and +U30 Net-_U26-Pad2_ Net-_U10-Pad3_ ? Net-_U1-Pad1_ Net-_U1-Pad13_ ? d_dff +U26 Net-_U25-Pad2_ Net-_U26-Pad2_ d_inverter +U31 Net-_U15-Pad1_ Net-_U1-Pad13_ Net-_U31-Pad3_ d_and +U35 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U35-Pad3_ d_and +U37 Net-_U1-Pad7_ Net-_U13-Pad2_ Net-_U36-Pad1_ d_and +U38 Net-_U34-Pad2_ Net-_U10-Pad3_ ? Net-_U1-Pad1_ Net-_U1-Pad12_ ? d_dff +U34 Net-_U33-Pad2_ Net-_U34-Pad2_ d_inverter +U2 Net-_U1-Pad9_ Net-_U13-Pad2_ d_inverter +U3 Net-_U1-Pad10_ Net-_U15-Pad1_ d_inverter +U4 Net-_U13-Pad2_ Net-_U15-Pad1_ Net-_U11-Pad2_ d_nor +U5 Net-_U15-Pad1_ Net-_U13-Pad2_ Net-_U10-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U12 Net-_U12-Pad1_ Net-_U11-Pad3_ Net-_U12-Pad3_ d_or +U7 Net-_U12-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ d_or +U8 Net-_U7-Pad3_ Net-_U8-Pad2_ d_inverter +U20 Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U16-Pad1_ d_or +U16 Net-_U16-Pad1_ Net-_U15-Pad3_ Net-_U16-Pad3_ d_or +U17 Net-_U16-Pad3_ Net-_U17-Pad2_ d_inverter +U28 Net-_U28-Pad1_ Net-_U27-Pad3_ Net-_U24-Pad1_ d_or +U24 Net-_U24-Pad1_ Net-_U23-Pad3_ Net-_U24-Pad3_ d_or +U25 Net-_U24-Pad3_ Net-_U25-Pad2_ d_inverter +U36 Net-_U36-Pad1_ Net-_U35-Pad3_ Net-_U32-Pad1_ d_or +U32 Net-_U32-Pad1_ Net-_U31-Pad3_ Net-_U32-Pad3_ d_or +U33 Net-_U32-Pad3_ Net-_U33-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir.out b/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir.out new file mode 100644 index 000000000..76caf8d3f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194.cir.out @@ -0,0 +1,160 @@ +* c:\users\ajay\onedrive\desktop\fossee2.3\esim\library\subcircuitlibrary\sn74ls194\sn74ls194.cir + +* u6 net-_u15-pad1_ net-_u1-pad2_ net-_u6-pad3_ d_and +* u11 net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u13 net-_u1-pad14_ net-_u13-pad2_ net-_u12-pad1_ d_and +* u14 net-_u14-pad1_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad15_ ? d_dff +* u9 net-_u8-pad2_ net-_u14-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad15_ net-_u15-pad3_ d_and +* u19 net-_u1-pad4_ net-_u11-pad2_ net-_u19-pad3_ d_and +* u21 net-_u1-pad13_ net-_u13-pad2_ net-_u20-pad1_ d_and +* u22 net-_u18-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad14_ ? d_dff +* u18 net-_u17-pad2_ net-_u18-pad2_ d_inverter +* u23 net-_u15-pad1_ net-_u1-pad14_ net-_u23-pad3_ d_and +* u27 net-_u1-pad5_ net-_u11-pad2_ net-_u27-pad3_ d_and +* u29 net-_u1-pad12_ net-_u13-pad2_ net-_u28-pad1_ d_and +* u30 net-_u26-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad13_ ? d_dff +* u26 net-_u25-pad2_ net-_u26-pad2_ d_inverter +* u31 net-_u15-pad1_ net-_u1-pad13_ net-_u31-pad3_ d_and +* u35 net-_u1-pad6_ net-_u11-pad2_ net-_u35-pad3_ d_and +* u37 net-_u1-pad7_ net-_u13-pad2_ net-_u36-pad1_ d_and +* u38 net-_u34-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad12_ ? d_dff +* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u13-pad2_ d_inverter +* u3 net-_u1-pad10_ net-_u15-pad1_ d_inverter +* u4 net-_u13-pad2_ net-_u15-pad1_ net-_u11-pad2_ d_nor +* u5 net-_u15-pad1_ net-_u13-pad2_ net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad11_ net-_u10-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u12-pad3_ d_or +* u7 net-_u12-pad3_ net-_u6-pad3_ net-_u7-pad3_ d_or +* u8 net-_u7-pad3_ net-_u8-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u16-pad1_ d_or +* u16 net-_u16-pad1_ net-_u15-pad3_ net-_u16-pad3_ d_or +* u17 net-_u16-pad3_ net-_u17-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u27-pad3_ net-_u24-pad1_ d_or +* u24 net-_u24-pad1_ net-_u23-pad3_ net-_u24-pad3_ d_or +* u25 net-_u24-pad3_ net-_u25-pad2_ d_inverter +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u32-pad1_ d_or +* u32 net-_u32-pad1_ net-_u31-pad3_ net-_u32-pad3_ d_or +* u33 net-_u32-pad3_ net-_u33-pad2_ d_inverter +a1 [net-_u15-pad1_ net-_u1-pad2_ ] net-_u6-pad3_ u6 +a2 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u1-pad14_ net-_u13-pad2_ ] net-_u12-pad1_ u13 +a4 net-_u14-pad1_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad15_ ? u14 +a5 net-_u8-pad2_ net-_u14-pad1_ u9 +a6 [net-_u15-pad1_ net-_u1-pad15_ ] net-_u15-pad3_ u15 +a7 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a8 [net-_u1-pad13_ net-_u13-pad2_ ] net-_u20-pad1_ u21 +a9 net-_u18-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad14_ ? u22 +a10 net-_u17-pad2_ net-_u18-pad2_ u18 +a11 [net-_u15-pad1_ net-_u1-pad14_ ] net-_u23-pad3_ u23 +a12 [net-_u1-pad5_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a13 [net-_u1-pad12_ net-_u13-pad2_ ] net-_u28-pad1_ u29 +a14 net-_u26-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad13_ ? u30 +a15 net-_u25-pad2_ net-_u26-pad2_ u26 +a16 [net-_u15-pad1_ net-_u1-pad13_ ] net-_u31-pad3_ u31 +a17 [net-_u1-pad6_ net-_u11-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u1-pad7_ net-_u13-pad2_ ] net-_u36-pad1_ u37 +a19 net-_u34-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad12_ ? u38 +a20 net-_u33-pad2_ net-_u34-pad2_ u34 +a21 net-_u1-pad9_ net-_u13-pad2_ u2 +a22 net-_u1-pad10_ net-_u15-pad1_ u3 +a23 [net-_u13-pad2_ net-_u15-pad1_ ] net-_u11-pad2_ u4 +a24 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u10-pad1_ u5 +a25 [net-_u10-pad1_ net-_u1-pad11_ ] net-_u10-pad3_ u10 +a26 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u12-pad3_ u12 +a27 [net-_u12-pad3_ net-_u6-pad3_ ] net-_u7-pad3_ u7 +a28 net-_u7-pad3_ net-_u8-pad2_ u8 +a29 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u16-pad1_ u20 +a30 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u16-pad3_ u16 +a31 net-_u16-pad3_ net-_u17-pad2_ u17 +a32 [net-_u28-pad1_ net-_u27-pad3_ ] net-_u24-pad1_ u28 +a33 [net-_u24-pad1_ net-_u23-pad3_ ] net-_u24-pad3_ u24 +a34 net-_u24-pad3_ net-_u25-pad2_ u25 +a35 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u32-pad1_ u36 +a36 [net-_u32-pad1_ net-_u31-pad3_ ] net-_u32-pad3_ u32 +a37 net-_u32-pad3_ net-_u33-pad2_ u33 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u38 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194.pro b/library/SubcircuitLibrary/SN74LS194/SN74LS194.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194.sch b/library/SubcircuitLibrary/SN74LS194/SN74LS194.sch new file mode 100644 index 000000000..42558e7a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194.sch @@ -0,0 +1,986 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS194-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 69397F7F +P 5200 3150 +F 0 "U6" H 5200 3150 60 0000 C CNN +F 1 "d_and" H 5250 3250 60 0000 C CNN +F 2 "" H 5200 3150 60 0000 C CNN +F 3 "" H 5200 3150 60 0000 C CNN + 1 5200 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U11 +U 1 1 69397F80 +P 5600 3150 +F 0 "U11" H 5600 3150 60 0000 C CNN +F 1 "d_and" H 5650 3250 60 0000 C CNN +F 2 "" H 5600 3150 60 0000 C CNN +F 3 "" H 5600 3150 60 0000 C CNN + 1 5600 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 69397F81 +P 6000 3150 +F 0 "U13" H 6000 3150 60 0000 C CNN +F 1 "d_and" H 6050 3250 60 0000 C CNN +F 2 "" H 6000 3150 60 0000 C CNN +F 3 "" H 6000 3150 60 0000 C CNN + 1 6000 3150 + 0 1 1 0 +$EndComp +$Comp +L d_dff U14 +U 1 1 69397F82 +P 6050 7900 +F 0 "U14" H 6050 7900 60 0000 C CNN +F 1 "d_dff" H 6050 8050 60 0000 C CNN +F 2 "" H 6050 7900 60 0000 C CNN +F 3 "" H 6050 7900 60 0000 C CNN + 1 6050 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 69397F83 +P 5300 7000 +F 0 "U9" H 5300 6900 60 0000 C CNN +F 1 "d_inverter" H 5300 7150 60 0000 C CNN +F 2 "" H 5350 6950 60 0000 C CNN +F 3 "" H 5350 6950 60 0000 C CNN + 1 5300 7000 + 0 1 1 0 +$EndComp +$Comp +L d_and U15 +U 1 1 69397F87 +P 6850 3150 +F 0 "U15" H 6850 3150 60 0000 C CNN +F 1 "d_and" H 6900 3250 60 0000 C CNN +F 2 "" H 6850 3150 60 0000 C CNN +F 3 "" H 6850 3150 60 0000 C CNN + 1 6850 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U19 +U 1 1 69397F88 +P 7250 3150 +F 0 "U19" H 7250 3150 60 0000 C CNN +F 1 "d_and" H 7300 3250 60 0000 C CNN +F 2 "" H 7250 3150 60 0000 C CNN +F 3 "" H 7250 3150 60 0000 C CNN + 1 7250 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U21 +U 1 1 69397F89 +P 7650 3150 +F 0 "U21" H 7650 3150 60 0000 C CNN +F 1 "d_and" H 7700 3250 60 0000 C CNN +F 2 "" H 7650 3150 60 0000 C CNN +F 3 "" H 7650 3150 60 0000 C CNN + 1 7650 3150 + 0 1 1 0 +$EndComp +$Comp +L d_dff U22 +U 1 1 69397F8A +P 7700 7900 +F 0 "U22" H 7700 7900 60 0000 C CNN +F 1 "d_dff" H 7700 8050 60 0000 C CNN +F 2 "" H 7700 7900 60 0000 C CNN +F 3 "" H 7700 7900 60 0000 C CNN + 1 7700 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 69397F8B +P 6950 7000 +F 0 "U18" H 6950 6900 60 0000 C CNN +F 1 "d_inverter" H 6950 7150 60 0000 C CNN +F 2 "" H 7000 6950 60 0000 C CNN +F 3 "" H 7000 6950 60 0000 C CNN + 1 6950 7000 + 0 1 1 0 +$EndComp +$Comp +L d_and U23 +U 1 1 69397F8F +P 8450 3150 +F 0 "U23" H 8450 3150 60 0000 C CNN +F 1 "d_and" H 8500 3250 60 0000 C CNN +F 2 "" H 8450 3150 60 0000 C CNN +F 3 "" H 8450 3150 60 0000 C CNN + 1 8450 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U27 +U 1 1 69397F90 +P 8850 3150 +F 0 "U27" H 8850 3150 60 0000 C CNN +F 1 "d_and" H 8900 3250 60 0000 C CNN +F 2 "" H 8850 3150 60 0000 C CNN +F 3 "" H 8850 3150 60 0000 C CNN + 1 8850 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U29 +U 1 1 69397F91 +P 9250 3150 +F 0 "U29" H 9250 3150 60 0000 C CNN +F 1 "d_and" H 9300 3250 60 0000 C CNN +F 2 "" H 9250 3150 60 0000 C CNN +F 3 "" H 9250 3150 60 0000 C CNN + 1 9250 3150 + 0 1 1 0 +$EndComp +$Comp +L d_dff U30 +U 1 1 69397F92 +P 9300 7900 +F 0 "U30" H 9300 7900 60 0000 C CNN +F 1 "d_dff" H 9300 8050 60 0000 C CNN +F 2 "" H 9300 7900 60 0000 C CNN +F 3 "" H 9300 7900 60 0000 C CNN + 1 9300 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 69397F93 +P 8550 7000 +F 0 "U26" H 8550 6900 60 0000 C CNN +F 1 "d_inverter" H 8550 7150 60 0000 C CNN +F 2 "" H 8600 6950 60 0000 C CNN +F 3 "" H 8600 6950 60 0000 C CNN + 1 8550 7000 + 0 1 1 0 +$EndComp +$Comp +L d_and U31 +U 1 1 69397F97 +P 10100 3150 +F 0 "U31" H 10100 3150 60 0000 C CNN +F 1 "d_and" H 10150 3250 60 0000 C CNN +F 2 "" H 10100 3150 60 0000 C CNN +F 3 "" H 10100 3150 60 0000 C CNN + 1 10100 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U35 +U 1 1 69397F98 +P 10500 3150 +F 0 "U35" H 10500 3150 60 0000 C CNN +F 1 "d_and" H 10550 3250 60 0000 C CNN +F 2 "" H 10500 3150 60 0000 C CNN +F 3 "" H 10500 3150 60 0000 C CNN + 1 10500 3150 + 0 1 1 0 +$EndComp +$Comp +L d_and U37 +U 1 1 69397F99 +P 10900 3150 +F 0 "U37" H 10900 3150 60 0000 C CNN +F 1 "d_and" H 10950 3250 60 0000 C CNN +F 2 "" H 10900 3150 60 0000 C CNN +F 3 "" H 10900 3150 60 0000 C CNN + 1 10900 3150 + 0 1 1 0 +$EndComp +$Comp +L d_dff U38 +U 1 1 69397F9A +P 10950 7900 +F 0 "U38" H 10950 7900 60 0000 C CNN +F 1 "d_dff" H 10950 8050 60 0000 C CNN +F 2 "" H 10950 7900 60 0000 C CNN +F 3 "" H 10950 7900 60 0000 C CNN + 1 10950 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 69397F9B +P 10200 7000 +F 0 "U34" H 10200 6900 60 0000 C CNN +F 1 "d_inverter" H 10200 7150 60 0000 C CNN +F 2 "" H 10250 6950 60 0000 C CNN +F 3 "" H 10250 6950 60 0000 C CNN + 1 10200 7000 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U2 +U 1 1 69397F9C +P 3050 1700 +F 0 "U2" H 3050 1600 60 0000 C CNN +F 1 "d_inverter" H 3050 1850 60 0000 C CNN +F 2 "" H 3100 1650 60 0000 C CNN +F 3 "" H 3100 1650 60 0000 C CNN + 1 3050 1700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 69397F9D +P 3050 2300 +F 0 "U3" H 3050 2200 60 0000 C CNN +F 1 "d_inverter" H 3050 2450 60 0000 C CNN +F 2 "" H 3100 2250 60 0000 C CNN +F 3 "" H 3100 2250 60 0000 C CNN + 1 3050 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 69397F9E +P 4000 2050 +F 0 "U4" H 4000 2050 60 0000 C CNN +F 1 "d_nor" H 4050 2150 60 0000 C CNN +F 2 "" H 4000 2050 60 0000 C CNN +F 3 "" H 4000 2050 60 0000 C CNN + 1 4000 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 69397F9F +P 4300 8650 +F 0 "U5" H 4300 8650 60 0000 C CNN +F 1 "d_and" H 4350 8750 60 0000 C CNN +F 2 "" H 4300 8650 60 0000 C CNN +F 3 "" H 4300 8650 60 0000 C CNN + 1 4300 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 69397FA0 +P 5350 8700 +F 0 "U10" H 5350 8700 60 0000 C CNN +F 1 "d_nor" H 5400 8800 60 0000 C CNN +F 2 "" H 5350 8700 60 0000 C CNN +F 3 "" H 5350 8700 60 0000 C CNN + 1 5350 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6939864E +P 3150 9200 +F 0 "U1" H 3200 9300 30 0000 C CNN +F 1 "PORT" H 3150 9200 30 0000 C CNN +F 2 "" H 3150 9200 60 0000 C CNN +F 3 "" H 3150 9200 60 0000 C CNN + 1 3150 9200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6939876F +P 4950 1200 +F 0 "U1" H 5000 1300 30 0000 C CNN +F 1 "PORT" H 4950 1200 30 0000 C CNN +F 2 "" H 4950 1200 60 0000 C CNN +F 3 "" H 4950 1200 60 0000 C CNN + 2 4950 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 693988A9 +P 5450 1200 +F 0 "U1" H 5500 1300 30 0000 C CNN +F 1 "PORT" H 5450 1200 30 0000 C CNN +F 2 "" H 5450 1200 60 0000 C CNN +F 3 "" H 5450 1200 60 0000 C CNN + 3 5450 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 69398938 +P 7100 1200 +F 0 "U1" H 7150 1300 30 0000 C CNN +F 1 "PORT" H 7100 1200 30 0000 C CNN +F 2 "" H 7100 1200 60 0000 C CNN +F 3 "" H 7100 1200 60 0000 C CNN + 4 7100 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 693989B9 +P 8700 1200 +F 0 "U1" H 8750 1300 30 0000 C CNN +F 1 "PORT" H 8700 1200 30 0000 C CNN +F 2 "" H 8700 1200 60 0000 C CNN +F 3 "" H 8700 1200 60 0000 C CNN + 5 8700 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 69398A42 +P 10350 1200 +F 0 "U1" H 10400 1300 30 0000 C CNN +F 1 "PORT" H 10350 1200 30 0000 C CNN +F 2 "" H 10350 1200 60 0000 C CNN +F 3 "" H 10350 1200 60 0000 C CNN + 6 10350 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 69398AD1 +P 11800 1550 +F 0 "U1" H 11850 1650 30 0000 C CNN +F 1 "PORT" H 11800 1550 30 0000 C CNN +F 2 "" H 11800 1550 60 0000 C CNN +F 3 "" H 11800 1550 60 0000 C CNN + 7 11800 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 69398B5A +P 8100 9700 +F 0 "U1" H 8150 9800 30 0000 C CNN +F 1 "PORT" H 8100 9700 30 0000 C CNN +F 2 "" H 8100 9700 60 0000 C CNN +F 3 "" H 8100 9700 60 0000 C CNN + 14 8100 9700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 69398BDD +P 1250 2300 +F 0 "U1" H 1300 2400 30 0000 C CNN +F 1 "PORT" H 1250 2300 30 0000 C CNN +F 2 "" H 1250 2300 60 0000 C CNN +F 3 "" H 1250 2300 60 0000 C CNN + 8 1250 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 69398C5C +P 2450 1700 +F 0 "U1" H 2500 1800 30 0000 C CNN +F 1 "PORT" H 2450 1700 30 0000 C CNN +F 2 "" H 2450 1700 60 0000 C CNN +F 3 "" H 2450 1700 60 0000 C CNN + 9 2450 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 69398CD7 +P 2450 2300 +F 0 "U1" H 2500 2400 30 0000 C CNN +F 1 "PORT" H 2450 2300 30 0000 C CNN +F 2 "" H 2450 2300 60 0000 C CNN +F 3 "" H 2450 2300 60 0000 C CNN + 10 2450 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69398D62 +P 3150 8850 +F 0 "U1" H 3200 8950 30 0000 C CNN +F 1 "PORT" H 3150 8850 30 0000 C CNN +F 2 "" H 3150 8850 60 0000 C CNN +F 3 "" H 3150 8850 60 0000 C CNN + 11 3150 8850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 69398DED +P 11350 9700 +F 0 "U1" H 11400 9800 30 0000 C CNN +F 1 "PORT" H 11350 9700 30 0000 C CNN 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net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u13 net-_u1-pad14_ net-_u13-pad2_ net-_u12-pad1_ d_and +* u14 net-_u14-pad1_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad15_ ? d_dff +* u9 net-_u8-pad2_ net-_u14-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad15_ net-_u15-pad3_ d_and +* u19 net-_u1-pad4_ net-_u11-pad2_ net-_u19-pad3_ d_and +* u21 net-_u1-pad13_ net-_u13-pad2_ net-_u20-pad1_ d_and +* u22 net-_u18-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad14_ ? d_dff +* u18 net-_u17-pad2_ net-_u18-pad2_ d_inverter +* u23 net-_u15-pad1_ net-_u1-pad14_ net-_u23-pad3_ d_and +* u27 net-_u1-pad5_ net-_u11-pad2_ net-_u27-pad3_ d_and +* u29 net-_u1-pad12_ net-_u13-pad2_ net-_u28-pad1_ d_and +* u30 net-_u26-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad13_ ? d_dff +* u26 net-_u25-pad2_ net-_u26-pad2_ d_inverter +* u31 net-_u15-pad1_ net-_u1-pad13_ net-_u31-pad3_ d_and +* u35 net-_u1-pad6_ net-_u11-pad2_ net-_u35-pad3_ d_and +* u37 net-_u1-pad7_ net-_u13-pad2_ net-_u36-pad1_ d_and +* u38 net-_u34-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad12_ ? d_dff +* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u13-pad2_ d_inverter +* u3 net-_u1-pad10_ net-_u15-pad1_ d_inverter +* u4 net-_u13-pad2_ net-_u15-pad1_ net-_u11-pad2_ d_nor +* u5 net-_u15-pad1_ net-_u13-pad2_ net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad11_ net-_u10-pad3_ d_nor +* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u12-pad3_ d_or +* u7 net-_u12-pad3_ net-_u6-pad3_ net-_u7-pad3_ d_or +* u8 net-_u7-pad3_ net-_u8-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u16-pad1_ d_or +* u16 net-_u16-pad1_ net-_u15-pad3_ net-_u16-pad3_ d_or +* u17 net-_u16-pad3_ net-_u17-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u27-pad3_ net-_u24-pad1_ d_or +* u24 net-_u24-pad1_ net-_u23-pad3_ net-_u24-pad3_ d_or +* u25 net-_u24-pad3_ net-_u25-pad2_ d_inverter +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u32-pad1_ d_or +* u32 net-_u32-pad1_ net-_u31-pad3_ net-_u32-pad3_ d_or +* u33 net-_u32-pad3_ net-_u33-pad2_ d_inverter +a1 [net-_u15-pad1_ net-_u1-pad2_ ] net-_u6-pad3_ u6 +a2 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u1-pad14_ net-_u13-pad2_ ] net-_u12-pad1_ u13 +a4 net-_u14-pad1_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad15_ ? u14 +a5 net-_u8-pad2_ net-_u14-pad1_ u9 +a6 [net-_u15-pad1_ net-_u1-pad15_ ] net-_u15-pad3_ u15 +a7 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a8 [net-_u1-pad13_ net-_u13-pad2_ ] net-_u20-pad1_ u21 +a9 net-_u18-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad14_ ? u22 +a10 net-_u17-pad2_ net-_u18-pad2_ u18 +a11 [net-_u15-pad1_ net-_u1-pad14_ ] net-_u23-pad3_ u23 +a12 [net-_u1-pad5_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a13 [net-_u1-pad12_ net-_u13-pad2_ ] net-_u28-pad1_ u29 +a14 net-_u26-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad13_ ? u30 +a15 net-_u25-pad2_ net-_u26-pad2_ u26 +a16 [net-_u15-pad1_ net-_u1-pad13_ ] net-_u31-pad3_ u31 +a17 [net-_u1-pad6_ net-_u11-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u1-pad7_ net-_u13-pad2_ ] net-_u36-pad1_ u37 +a19 net-_u34-pad2_ net-_u10-pad3_ ? net-_u1-pad1_ net-_u1-pad12_ ? u38 +a20 net-_u33-pad2_ net-_u34-pad2_ u34 +a21 net-_u1-pad9_ net-_u13-pad2_ u2 +a22 net-_u1-pad10_ net-_u15-pad1_ u3 +a23 [net-_u13-pad2_ net-_u15-pad1_ ] net-_u11-pad2_ u4 +a24 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u10-pad1_ u5 +a25 [net-_u10-pad1_ net-_u1-pad11_ ] net-_u10-pad3_ u10 +a26 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u12-pad3_ u12 +a27 [net-_u12-pad3_ net-_u6-pad3_ ] net-_u7-pad3_ u7 +a28 net-_u7-pad3_ net-_u8-pad2_ u8 +a29 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u16-pad1_ u20 +a30 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u16-pad3_ u16 +a31 net-_u16-pad3_ net-_u17-pad2_ u17 +a32 [net-_u28-pad1_ net-_u27-pad3_ ] net-_u24-pad1_ u28 +a33 [net-_u24-pad1_ net-_u23-pad3_ ] net-_u24-pad3_ u24 +a34 net-_u24-pad3_ net-_u25-pad2_ u25 +a35 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u32-pad1_ u36 +a36 [net-_u32-pad1_ net-_u31-pad3_ ] net-_u32-pad3_ u32 +a37 net-_u32-pad3_ net-_u33-pad2_ u33 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u38 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS194 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/SN74LS194_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS194/SN74LS194_Previous_Values.xml new file mode 100644 index 000000000..2528aa16d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/SN74LS194_Previous_Values.xml @@ -0,0 +1 @@ +d_srffd_inverterd_inverterd_srffd_inverterd_srffd_inverterd_inverterd_inverterd_srffd_nandd_nandd_nord_inverterd_nandd_nandd_nord_inverterd_nandd_nandd_nord_inverterd_nandd_nandd_nord_inverterd_inverterd_inverterd_inverterd_dffd_dffd_dffd_dffd_ord_ord_andd_andd_andd_dffd_ord_ord_inverterd_andd_andd_andd_dffd_inverterd_ord_ord_inverterd_andd_andd_andd_dffd_ord_ord_inverterd_andd_andd_andd_dffd_inverterd_nord_andd_nortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS194/analysis b/library/SubcircuitLibrary/SN74LS194/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS194/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file